A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator

In this article, we propose a digital-to-time conversion technique operating entirely in the sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal’s final slicing into the time domain of a programmably delayed clock. Precise timing delay is obtained simply by adjusting the dc offset of the sine signal. A low-complexity sinusoidal-like predistortion linearizes its transfer function. The technique merges the functionality of a digital-to-time converter (DTC) with an XO generation, thus drastically reducing the power consumption of the targeted subsystem while offering a wide range with fine resolution, low noise, and high linearity. Without the requirement for a power-hungry reference buffer/slicer, the proposed DTC benefits from the raw XO waveform, resulting in a large delay coverage and fine resolution. Fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS, the prototype of XO+DTC consumes only 0.52mW while achieving a 546-ps range with a fine resolution of 266 fs. Its rms jitter (integrated from 1 kHz to 10 MHz) is only 86.6 fs at the output frequency of 100 MHz. Using predistortion of only the fundamental harmonic of a prestored sinusoidal lookup table (LUT), the measured integral nonlinearity (INL) is reduced to +2/−1.9 ps. Together with a higher-harmonic content, such as the second to fourth harmonics, the peak-to-peak INL and DNL is brought down to within ±1 LSB (i.e., 266 fs). Based on system modeling of a DTC-assisted all-digital phase-locked loop (ADPLL), the simulated in-band fractional spur (IBFS) can be as low as −66 dBc.