从$-$25 $^{\circ}$C到$ 85 $^{\circ}$C,具有自动校准定时控制的高效超声能量收集接口

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Guangshu Zhao;Chao Xie;Chenxi Wang;Milin Zhang;Man-Kay Law
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引用次数: 0

摘要

本文章由计算机程序翻译,如有差异,请以英文原文为准。
High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From −25 °C to 85 °C
This work presents a high-efficiency ultrasound energy harvesting interface with auto-calibrated timing control, featuring: 1) the proposed $C_{\text {P}}$ auto-calibration, consisting of the half bias-flip time ( $t_{\text {half}}$ ) detection and adaptive closed-loop time calibration (ACTC) to improve the system’s robustness against piezoelectric transducer (PZT) materials and environmental variations; 2) the proposed charge recycling (CR) bootstrapping driver to reduce conduction loss and improve the $C_{\text {P}}$ auto-calibration accuracy as well as the peak voltage flipping efficiency ( $\eta _{\text {flip}}$ ); and 3) the proposed coarse detection and fine calibration technique to eliminate the inherent timing offset and increase the acceptable input excitation frequency range. The fabricated chip prototype in 0.18- $\mu $ m silicon on insulator (SOI) CMOS process can adapt to both PZT5A (nominal ${C_{\text {P}}}~{\sim }~114$ pF) and PZT5H (nominal ${C_{\text {P}}}~{\sim }~190$ pF) and is capable of operating over a wide temperature range from ${-} 25~{^{\circ }}$ C to $85~{^{\circ }}$ C. The proposed $C_{\text {P}}$ auto-calibration and CR bootstrapping driver can improve the $\eta _{\text {flip}}$ to as high as 93.6% at an output power of $496.6~{\mu }$ W. With the proposed coarse detection and fine calibration technique, this work demonstrates a high measured peak power conversion efficiency (PCE) of 94.5%, corresponding to a ~23% improvement when compared with the prior ultrasound energy harvesting interface while achieving a favorable figure of merit (FoM) of $8.13{\times }$ .
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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