一种新型的双沟槽SiC sbd嵌入式MOSFET，具有改进的性能因数和短路坚固性

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-11-22 DOI:10.1016/j.mejo.2024.106495

Ziwei Hu , Jiafei Yao , Fan Yang , Yuxuan Dai , Kemeng Yang , Man Li , Jing Chen , Maolin Zhang , Jun Zhang , Yufeng Guo

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引用次数: 0

摘要

提出并研究了一种新型的1.2 kv双沟槽肖特基势垒二极管（dsss - mos） MOSFET。该器件采用填充高k介电介质的深栅极沟槽和阶梯形SBD的浅源沟槽来调制电场分布，从而获得更高的品质系数（FOM）。优化结构参数后，与平面栅极MOSFET （PG-MOS）和沟栅MOSFET （TG-MOS）相比，DTSS-MOS的fet分别提高了266%和47%。同时，由于其较低的比导通电阻（Ron,sp）， DTSS-MOS表现出出色的高频优值（HFFOM）。此外，较浅的源沟槽采用了阶梯形SBD，使得P阱区和P+屏蔽层有效地减少了SBD区内的电子流动路径，从而降低了温度，提高了抗短路时间（SCWT）。与PG-MOS和TG-MOS相比，DTSS-MOS的SCWT分别提高了75%和133%。此外，还提供了一种可行的DTSS-MOS工艺流程。

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A novel double-trench SiC SBD-embedded MOSFET with improved figure-of-merit and short-circuit ruggedness

A novel 1.2-kV double-trench SiC MOSFET with stepped Schottky barrier diode (SBD) (DTSS-MOS) has been proposed and studied. The proposed device employs a deep gate trench filled with high-K dielectric and a shallow source trench with stepped SBD to modulate the electric field distribution, causing a higher figure-of-merit (FOM). After optimizing the structural parameters, the FOM of the DTSS-MOS improves by 266 % and 47 % compared to the planar-gate MOSFET (PG-MOS) and the trench-gate MOSFET (TG-MOS), respectively. Meanwhile, due to its lower specific on-resistance (R_on,sp), the DTSS-MOS exhibits an outstanding high-frequency figure of merit (HFFOM). Furthermore, the shallow source trench incorporates the stepped SBD, allowing the P-well region and P+ shielding layer to effectively reduce the electron flowing path in the SBD region, thereby lowering the temperature and enhancing the short-circuit withstand time (SCWT). The SCWT of the DTSS-MOS is increased by 75 % and 133 % compared with PG-MOS and TG-MOS, respectively. Additionally, a feasible process flow for the DTSS-MOS is provided.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.