7.3-14.2 GHz 6.3 mW LNA,增益9.4±0.6 dB,采用变压器反馈和峰值增益分布

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Yuanrong Xie, Jincai Wen
{"title":"7.3-14.2 GHz 6.3 mW LNA,增益9.4±0.6 dB,采用变压器反馈和峰值增益分布","authors":"Yuanrong Xie,&nbsp;Jincai Wen","doi":"10.1016/j.mejo.2024.106497","DOIUrl":null,"url":null,"abstract":"<div><div>This article presents a wideband low-noise amplifier (LNA) with low power consumption and flat gain, implemented in a 180 nm CMOS technology. This LNA uses low voltage operation and current-reuse technology to reduce power consumption, and its cascaded structure is composed of a common-source (CS) stage with gate-source transformer feedback and a cascode stage. The T-coil structure is employed for inter-stage and output matching to expand bandwidth and adjust peak gain, while achieving in-band flat gain through the peak gain distribution technology. Measured results show that the LNA achieves a flat gain of 9.4 ± 0.6 dB over the 7.3–14.2 GHz frequency band, with a 3 dB bandwidth of 6.3–14.6 GHz and an in-band noise figure (NF) of lower than 4.2 dB. The core chip area is 0.29 mm<sup>2</sup>, and the power consumption is only 6.3 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106497"},"PeriodicalIF":1.9000,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 7.3–14.2 GHz 6.3 mW LNA with 9.4±0.6 dB gain using transformer feedback and peak-gain distribution\",\"authors\":\"Yuanrong Xie,&nbsp;Jincai Wen\",\"doi\":\"10.1016/j.mejo.2024.106497\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This article presents a wideband low-noise amplifier (LNA) with low power consumption and flat gain, implemented in a 180 nm CMOS technology. This LNA uses low voltage operation and current-reuse technology to reduce power consumption, and its cascaded structure is composed of a common-source (CS) stage with gate-source transformer feedback and a cascode stage. The T-coil structure is employed for inter-stage and output matching to expand bandwidth and adjust peak gain, while achieving in-band flat gain through the peak gain distribution technology. Measured results show that the LNA achieves a flat gain of 9.4 ± 0.6 dB over the 7.3–14.2 GHz frequency band, with a 3 dB bandwidth of 6.3–14.6 GHz and an in-band noise figure (NF) of lower than 4.2 dB. The core chip area is 0.29 mm<sup>2</sup>, and the power consumption is only 6.3 mW.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"155 \",\"pages\":\"Article 106497\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-11-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124002017\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124002017","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种采用180nm CMOS技术实现的低功耗、平坦增益的宽带低噪声放大器(LNA)。该LNA采用低电压工作和电流复用技术来降低功耗,其级联结构由具有栅极源变压器反馈的共源级和级联级组成。采用t线圈结构进行级间和输出匹配,扩大带宽,调节峰值增益,同时通过峰值增益分配技术实现带内平坦增益。测量结果表明,该LNA在7.3 ~ 14.2 GHz频段内的平坦增益为9.4±0.6 dB, 3db带宽为6.3 ~ 14.6 GHz,带内噪声系数(NF)低于4.2 dB。核心芯片面积为0.29 mm2,功耗仅为6.3 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 7.3–14.2 GHz 6.3 mW LNA with 9.4±0.6 dB gain using transformer feedback and peak-gain distribution
This article presents a wideband low-noise amplifier (LNA) with low power consumption and flat gain, implemented in a 180 nm CMOS technology. This LNA uses low voltage operation and current-reuse technology to reduce power consumption, and its cascaded structure is composed of a common-source (CS) stage with gate-source transformer feedback and a cascode stage. The T-coil structure is employed for inter-stage and output matching to expand bandwidth and adjust peak gain, while achieving in-band flat gain through the peak gain distribution technology. Measured results show that the LNA achieves a flat gain of 9.4 ± 0.6 dB over the 7.3–14.2 GHz frequency band, with a 3 dB bandwidth of 6.3–14.6 GHz and an in-band noise figure (NF) of lower than 4.2 dB. The core chip area is 0.29 mm2, and the power consumption is only 6.3 mW.
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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