Feng Bu , Ruixue Ding , Depeng Sun , Yuan Gao , Ruiqing Wang , Xiaoteng Zhao , Rong Zhou , Shubin Liu
{"title":"1 V 3.9-5.2 GHz 基准采样 PLL,具有 168-fsrms 集成抖动和 -76-dBc 基准杂散","authors":"Feng Bu , Ruixue Ding , Depeng Sun , Yuan Gao , Ruiqing Wang , Xiaoteng Zhao , Rong Zhou , Shubin Liu","doi":"10.1016/j.mejo.2024.106483","DOIUrl":null,"url":null,"abstract":"<div><div>This letter presents a low-voltage (LV), low-jitter reference-sampling phase-locked loop (RSPLL), which can achieve sub-200-fs jitter performance with a 1-V supply voltage. With the proposed level-shift-up reference-sampling phase detector (RSPD), the on-resistance of sample and hold (SH) switches is reduced, and it ensures the integrity of the reference signal. Fabricated in the 180-nm RF CMOS process, the area of the chip is about 445 × 775 <span><math><mrow><mi>μ</mi></mrow></math></span> m<sup>2</sup>. The proposed RSPLL can achieve −135-dBc/Hz@10 MHz phase noise and −76.15-dBc reference spur at 4.58 GHz with 1-V supply voltage. The rms jitter is 168.3 fs integrated from 10 kHz to 100 MHz, and the power consumption is 9.66 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106483"},"PeriodicalIF":1.9000,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1-V 3.9–5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and −76-dBc reference spur\",\"authors\":\"Feng Bu , Ruixue Ding , Depeng Sun , Yuan Gao , Ruiqing Wang , Xiaoteng Zhao , Rong Zhou , Shubin Liu\",\"doi\":\"10.1016/j.mejo.2024.106483\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This letter presents a low-voltage (LV), low-jitter reference-sampling phase-locked loop (RSPLL), which can achieve sub-200-fs jitter performance with a 1-V supply voltage. With the proposed level-shift-up reference-sampling phase detector (RSPD), the on-resistance of sample and hold (SH) switches is reduced, and it ensures the integrity of the reference signal. Fabricated in the 180-nm RF CMOS process, the area of the chip is about 445 × 775 <span><math><mrow><mi>μ</mi></mrow></math></span> m<sup>2</sup>. The proposed RSPLL can achieve −135-dBc/Hz@10 MHz phase noise and −76.15-dBc reference spur at 4.58 GHz with 1-V supply voltage. The rms jitter is 168.3 fs integrated from 10 kHz to 100 MHz, and the power consumption is 9.66 mW.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"155 \",\"pages\":\"Article 106483\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124001875\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001875","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 1-V 3.9–5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and −76-dBc reference spur
This letter presents a low-voltage (LV), low-jitter reference-sampling phase-locked loop (RSPLL), which can achieve sub-200-fs jitter performance with a 1-V supply voltage. With the proposed level-shift-up reference-sampling phase detector (RSPD), the on-resistance of sample and hold (SH) switches is reduced, and it ensures the integrity of the reference signal. Fabricated in the 180-nm RF CMOS process, the area of the chip is about 445 × 775 m2. The proposed RSPLL can achieve −135-dBc/Hz@10 MHz phase noise and −76.15-dBc reference spur at 4.58 GHz with 1-V supply voltage. The rms jitter is 168.3 fs integrated from 10 kHz to 100 MHz, and the power consumption is 9.66 mW.
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