{"title":"通过优化脉冲模式降低直流链路电压纹波,提高电动汽车牵引逆变器的功率密度","authors":"Maximilian Hepp;Michael Saur;Mark-M. Bakran","doi":"10.1109/OJPEL.2024.3493169","DOIUrl":null,"url":null,"abstract":"The DC-link capacitor represents a critical component in electric vehicle traction inverters, given that it constitutes the largest single volume within a traction inverter. The DC-link capacitance must be selected carefully, to ensure that the voltage ripple remains within defined limits, as this has a direct impact on the design of other components connected to the high voltage bus. Typical approaches attempt to reduce the required DC-link capacitance by increasing the pulse width modulation (PWM) switching frequency. However, this leads to a compromise as higher switching frequencies can cause additional losses, potentially necessitating a larger area for costly silicon carbide (SiC) semiconductors. In this contribution, optimized pulse patterns (OPPs) are proposed as a solution to improve the DC-link voltage ripple, allowing a reduction in capacitor size and a significant decrease in switching frequency compared to the standard Space-Vector PWM. The paper outlines the mathematical methods for simulating and designing the DC-link regarding voltage ripple and current stress. It compares the simulations for Space-Vector PWM and OPPs, leading to the development of two distinct capacitor designs. The theoretical 20% reduction in the volume of the DC-link capacitor is confirmed through experimental validation on a 250 kW machine test bench setup.","PeriodicalId":93182,"journal":{"name":"IEEE open journal of power electronics","volume":"5 ","pages":"1767-1781"},"PeriodicalIF":5.0000,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10746599","citationCount":"0","resultStr":"{\"title\":\"Reducing the DC-Link Voltage Ripple by Optimized Pulse Patterns to Increase the Power Density of Traction Inverters in Electric Vehicles\",\"authors\":\"Maximilian Hepp;Michael Saur;Mark-M. Bakran\",\"doi\":\"10.1109/OJPEL.2024.3493169\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The DC-link capacitor represents a critical component in electric vehicle traction inverters, given that it constitutes the largest single volume within a traction inverter. The DC-link capacitance must be selected carefully, to ensure that the voltage ripple remains within defined limits, as this has a direct impact on the design of other components connected to the high voltage bus. Typical approaches attempt to reduce the required DC-link capacitance by increasing the pulse width modulation (PWM) switching frequency. However, this leads to a compromise as higher switching frequencies can cause additional losses, potentially necessitating a larger area for costly silicon carbide (SiC) semiconductors. In this contribution, optimized pulse patterns (OPPs) are proposed as a solution to improve the DC-link voltage ripple, allowing a reduction in capacitor size and a significant decrease in switching frequency compared to the standard Space-Vector PWM. The paper outlines the mathematical methods for simulating and designing the DC-link regarding voltage ripple and current stress. It compares the simulations for Space-Vector PWM and OPPs, leading to the development of two distinct capacitor designs. The theoretical 20% reduction in the volume of the DC-link capacitor is confirmed through experimental validation on a 250 kW machine test bench setup.\",\"PeriodicalId\":93182,\"journal\":{\"name\":\"IEEE open journal of power electronics\",\"volume\":\"5 \",\"pages\":\"1767-1781\"},\"PeriodicalIF\":5.0000,\"publicationDate\":\"2024-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10746599\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE open journal of power electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10746599/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE open journal of power electronics","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10746599/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Reducing the DC-Link Voltage Ripple by Optimized Pulse Patterns to Increase the Power Density of Traction Inverters in Electric Vehicles
The DC-link capacitor represents a critical component in electric vehicle traction inverters, given that it constitutes the largest single volume within a traction inverter. The DC-link capacitance must be selected carefully, to ensure that the voltage ripple remains within defined limits, as this has a direct impact on the design of other components connected to the high voltage bus. Typical approaches attempt to reduce the required DC-link capacitance by increasing the pulse width modulation (PWM) switching frequency. However, this leads to a compromise as higher switching frequencies can cause additional losses, potentially necessitating a larger area for costly silicon carbide (SiC) semiconductors. In this contribution, optimized pulse patterns (OPPs) are proposed as a solution to improve the DC-link voltage ripple, allowing a reduction in capacitor size and a significant decrease in switching frequency compared to the standard Space-Vector PWM. The paper outlines the mathematical methods for simulating and designing the DC-link regarding voltage ripple and current stress. It compares the simulations for Space-Vector PWM and OPPs, leading to the development of two distinct capacitor designs. The theoretical 20% reduction in the volume of the DC-link capacitor is confirmed through experimental validation on a 250 kW machine test bench setup.