40 nm CMOS 低噪声仪器放大器，带用于神经信号采集的正反馈回路和直流伺服回路

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-11-06 DOI:10.1016/j.vlsi.2024.102304

Shuoshuo Zhu, Bin Wang, Xiaokun Lin, Lu Liu, Xiao Qu, Weitao Yang

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引用次数: 0

摘要

本文介绍了一种用于神经信号采集的低噪声仪器放大器（LNA）。拟议的 LNA 由两个运算跨导放大器 (OTA)、反馈环路、正反馈环路 (PFL)、直流伺服环路 (DSL) 以及位于电容反馈环路和运算放大器之间的内部斩波开关组成。LNA 采用带内部斩波器的电容耦合放大器，以获得轨至轨电极直流偏移 (EDO) 抑制能力，并消除 OTA 的闪烁噪声。PFL 的设计旨在改善电路的输入阻抗，而 DSL 的引入则是为了抑制斩波器开关引入的残余偏移。该 LNA 采用 0.69 × 0.1 mm2 的 40 nm CMOS 技术实现，电源电压为 2.5 V，电流为 7.4 μA，在 1-200 Hz 频率范围内，对于低频、低振幅神经信号的输入参考噪声（IRN）为 1.69 μVrms。此外，仿真结果表明，该 LNA 在 50 Hz 时实现了 87.12 dB 的共模抑制比 (CMRR)、87.64 dB 的电源抑制比 (PSRR) 和 2.75 GΩ 的输入阻抗。

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A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition

This paper presents a low-noise instrument amplifier (LNA) for neural signal acquisition. The proposed LNA consists of two operational transconductance amplifiers (OTA), feedback loops, a positive feedback loop (PFL), a DC servo loop (DSL) and the internal chopper switch located between the capacitive feedback loop and op-amp. The LNA employs the capacitively coupled amplifier with the internal chopper to obtain the rail to rail electrode dc offset (EDO) rejection ability and eliminate the flicker noise of OTA. The PFL is designed to improve the input impedance of the circuit, and the DSL is introduced to suppress the residual offset introduced by the chopper switch. Realized in a 40 nm CMOS technology with 0.69 × 0.1 mm², the LNA draws 7.4 μA from a supply voltage of 2.5Vand exhibits 1.69 μVrms input-referred noise (IRN) over 1–200 Hz for low frequency and low amplitude neural signals. Besides, the simulation results show that the LNA achieves 87.12 dB common-mode rejection ratio (CMRR), 87.64 dB power-supply rejection ratio (PSRR) and 2.75 GΩ input impedance at 50 Hz.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.