Study of Delay Instabilities in Xilinx FPGA-Embedded Multigigabit Transceivers for Clock Distribution and Synchronization

Multigigabit transceivers (MGTs) of Xilinx field-programmable gate arrays (FPGAs) have been widely investigated for the implementation of clock distribution and synchronization systems in physics experiments. Often, the proposed solutions are based on the clock signal recovered from the serial stream. However, since the main purpose of MGTs in FPGA is to achieve high-speed data transmission, the delay stability, especially after initialization/reset operations, is not sufficiently considered. The Xilinx MGTs can be configured in different modes for flexibility. Since Xilinx does not fully explain the implementation structure of each mode, the delay characteristics must be investigated experimentally to achieve high-performance clock transmission. This article presents a comprehensive investigation of the delay instabilities in Xilinx MGTs and proposes countermeasures to minimize them for stable clock and data transmission. In addition, a method is proposed to obtain a high-quality recovered clock directly from Xilinx UltraScale and higher-level FPGAs, eliminating the need for an off-chip jitter cleaner. The test results indicate that high clock distribution and synchronization performance can be achieved over the MGT-based serial link once the delay instabilities are properly addressed.