{"title":"连续时间 ADC 基础知识:第二部分:连续时间三角积分转换器","authors":"Shanthi Pavan","doi":"10.1109/MSSC.2024.3443249","DOIUrl":null,"url":null,"abstract":"The first part of this two-article series described the continuous-time pipelined (CTP) ADC, which is appropriate when the oversampling ratio (OSR) is small. When the OSR is large, it becomes feasible to embed the quantizer into the antialias filter’s feedback loop. Such sub-systems are referred to as continuous-time delta-sigma modulators. This article describes the ideas behind such analog-to-digital converters.","PeriodicalId":100636,"journal":{"name":"IEEE Solid-State Circuits Magazine","volume":"16 4","pages":"76-82"},"PeriodicalIF":0.0000,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fundamentals of Continuous-Time ADCs: Part Two: Continuous-Time Delta–Sigma Converters\",\"authors\":\"Shanthi Pavan\",\"doi\":\"10.1109/MSSC.2024.3443249\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The first part of this two-article series described the continuous-time pipelined (CTP) ADC, which is appropriate when the oversampling ratio (OSR) is small. When the OSR is large, it becomes feasible to embed the quantizer into the antialias filter’s feedback loop. Such sub-systems are referred to as continuous-time delta-sigma modulators. This article describes the ideas behind such analog-to-digital converters.\",\"PeriodicalId\":100636,\"journal\":{\"name\":\"IEEE Solid-State Circuits Magazine\",\"volume\":\"16 4\",\"pages\":\"76-82\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Magazine\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10752800/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Magazine","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10752800/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fundamentals of Continuous-Time ADCs: Part Two: Continuous-Time Delta–Sigma Converters
The first part of this two-article series described the continuous-time pipelined (CTP) ADC, which is appropriate when the oversampling ratio (OSR) is small. When the OSR is large, it becomes feasible to embed the quantizer into the antialias filter’s feedback loop. Such sub-systems are referred to as continuous-time delta-sigma modulators. This article describes the ideas behind such analog-to-digital converters.