Enhancing disturbance rejection in boost converter for CPL: A controller design approach with partial pole placement and approximate model matching.

In DC microgrids, the cascade operation of the DC-DC converters leads to a constant power load fed by the boost converter, resulting in unstable behavior in addition to the non-minimum phase dynamics. An enhanced load disturbance rejection control scheme based on partial pole placement and an approximate model matching technique is proposed. This approach is inspired by the well-known direct synthesis method to achieve optimal load disturbance rejection performance. The effectiveness of the proposed control scheme has been validated through hardware implementation, demonstrating its capability in setpoint tracking and load disturbance rejection under variations in load power and input voltage. The robust stability of the suggested scheme has been investigated through the Kharitonov theorem and Monte-Carlo simulation, considering different performance matrices. The suitability of the presented scheme has been established by analyzing the comparative performance of recently reported works. The proposed controller reduces peak overshoot and settling time by ∼50%, handles system uncertainties up to 75%, and outperforms FOPID controllers tuned with particle swarm optimization, queen bee genetic algorithm, and chaos game optimization methods.