使用可重构反馈机制的无掺杂和无电容 1T-DRAM 单元。

IF 2.9 4区 材料科学 Q3 MATERIALS SCIENCE, MULTIDISCIPLINARY
Yuna Suh, Doohyeok Lim
{"title":"使用可重构反馈机制的无掺杂和无电容 1T-DRAM 单元。","authors":"Yuna Suh, Doohyeok Lim","doi":"10.1088/1361-6528/ad902c","DOIUrl":null,"url":null,"abstract":"<p><p>In this paper, we propose a doping- and capacitor-less 1T-DRAM cell, which achieved virtual doping by leveraging charge plasma and bias-induced electrostatic doping (bias-ED) techniques in a 5 nm-thick intrinsic silicon body, thereby eliminating doping processes. Platinum was in contact with the drain, while aluminum was in contact with the source, enabling virtual doping of the silicon body into a<i>p</i>*-<i>i-n</i>* configuration via the charge-plasma technique. Two coupled polarity gates and one control gate are positioned above the intrinsic channel region. The intrinsic channel region is virtually doped through the bias-ED by applying voltages to the gates, forming potential wells inside the channel. The voltage applied to the two coupled polarity gates determines whether the device operates in the<i>p</i>- or<i>n</i>-channel mode, whereas the control gate governs the flow of charge carriers. Charge carriers are stored and released in the potential wells inside the channel by adjusting the gate, effectively replacing the capacitor. In this device, the placement of polarity gates on either side of the control gate enables the observation of the reconfigurable characteristics. Moreover, the proposed device utilizes a feedback mechanism, enabling excellent memory characteristics such as a high on/off current ratio of ∼10<sup>9</sup>, steep switching behavior of ∼0.2<i>µ</i>V dec<sup>-1</sup>, short write time of 10 ns, long hold retention of over 100 s, and long read retention of over 600 s.</p>","PeriodicalId":19035,"journal":{"name":"Nanotechnology","volume":" ","pages":""},"PeriodicalIF":2.9000,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Doping- and capacitor-less 1T-DRAM cell using reconfigurable feedback mechanism.\",\"authors\":\"Yuna Suh, Doohyeok Lim\",\"doi\":\"10.1088/1361-6528/ad902c\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>In this paper, we propose a doping- and capacitor-less 1T-DRAM cell, which achieved virtual doping by leveraging charge plasma and bias-induced electrostatic doping (bias-ED) techniques in a 5 nm-thick intrinsic silicon body, thereby eliminating doping processes. Platinum was in contact with the drain, while aluminum was in contact with the source, enabling virtual doping of the silicon body into a<i>p</i>*-<i>i-n</i>* configuration via the charge-plasma technique. Two coupled polarity gates and one control gate are positioned above the intrinsic channel region. The intrinsic channel region is virtually doped through the bias-ED by applying voltages to the gates, forming potential wells inside the channel. The voltage applied to the two coupled polarity gates determines whether the device operates in the<i>p</i>- or<i>n</i>-channel mode, whereas the control gate governs the flow of charge carriers. Charge carriers are stored and released in the potential wells inside the channel by adjusting the gate, effectively replacing the capacitor. In this device, the placement of polarity gates on either side of the control gate enables the observation of the reconfigurable characteristics. Moreover, the proposed device utilizes a feedback mechanism, enabling excellent memory characteristics such as a high on/off current ratio of ∼10<sup>9</sup>, steep switching behavior of ∼0.2<i>µ</i>V dec<sup>-1</sup>, short write time of 10 ns, long hold retention of over 100 s, and long read retention of over 600 s.</p>\",\"PeriodicalId\":19035,\"journal\":{\"name\":\"Nanotechnology\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2024-11-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nanotechnology\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://doi.org/10.1088/1361-6528/ad902c\",\"RegionNum\":4,\"RegionCategory\":\"材料科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"MATERIALS SCIENCE, MULTIDISCIPLINARY\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nanotechnology","FirstCategoryId":"88","ListUrlMain":"https://doi.org/10.1088/1361-6528/ad902c","RegionNum":4,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"MATERIALS SCIENCE, MULTIDISCIPLINARY","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种无掺杂和无电容的 1T-DRAM 电池,它利用电荷等离子体和偏压诱导静电掺杂(bias-ED)技术在 5 纳米厚的本征硅体中实现了虚拟掺杂,从而消除了掺杂过程。铂与漏极接触,而铝与源极接触,从而通过电荷等离子体技术将硅体虚拟掺杂成 p*-i-n* 结构。两个耦合极性栅极和一个控制栅极位于本征沟道区上方。通过向栅极施加电压,在沟道内形成电位井,从而通过偏置电解槽对本征沟道区进行虚拟掺杂。施加在两个耦合极性栅极上的电压决定了器件是以 p 沟道模式还是 n 沟道模式工作,而控制栅极则控制电荷载流子的流动。电荷载流子通过调节栅极在沟道内的电位井中存储和释放,从而有效地取代了电容器。在该器件中,将极性栅极置于控制栅极的两侧可以观察到可重新配置的特性。此外,该器件还采用了反馈机制,从而实现了卓越的存储器特性,如约 10^9 的高导通/关断电流比、约 0.2 µV/dec 的陡峭开关行为、10 ns 的短写入时间、100 s 以上的长保持时间和 600 s 以上的长读取时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Doping- and capacitor-less 1T-DRAM cell using reconfigurable feedback mechanism.

In this paper, we propose a doping- and capacitor-less 1T-DRAM cell, which achieved virtual doping by leveraging charge plasma and bias-induced electrostatic doping (bias-ED) techniques in a 5 nm-thick intrinsic silicon body, thereby eliminating doping processes. Platinum was in contact with the drain, while aluminum was in contact with the source, enabling virtual doping of the silicon body into ap*-i-n* configuration via the charge-plasma technique. Two coupled polarity gates and one control gate are positioned above the intrinsic channel region. The intrinsic channel region is virtually doped through the bias-ED by applying voltages to the gates, forming potential wells inside the channel. The voltage applied to the two coupled polarity gates determines whether the device operates in thep- orn-channel mode, whereas the control gate governs the flow of charge carriers. Charge carriers are stored and released in the potential wells inside the channel by adjusting the gate, effectively replacing the capacitor. In this device, the placement of polarity gates on either side of the control gate enables the observation of the reconfigurable characteristics. Moreover, the proposed device utilizes a feedback mechanism, enabling excellent memory characteristics such as a high on/off current ratio of ∼109, steep switching behavior of ∼0.2µV dec-1, short write time of 10 ns, long hold retention of over 100 s, and long read retention of over 600 s.

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来源期刊
Nanotechnology
Nanotechnology 工程技术-材料科学:综合
CiteScore
7.10
自引率
5.70%
发文量
820
审稿时长
2.5 months
期刊介绍: The journal aims to publish papers at the forefront of nanoscale science and technology and especially those of an interdisciplinary nature. Here, nanotechnology is taken to include the ability to individually address, control, and modify structures, materials and devices with nanometre precision, and the synthesis of such structures into systems of micro- and macroscopic dimensions such as MEMS based devices. It encompasses the understanding of the fundamental physics, chemistry, biology and technology of nanometre-scale objects and how such objects can be used in the areas of computation, sensors, nanostructured materials and nano-biotechnology.
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