{"title":"用于存储器接口的基于加权-VREF 的环路未展开 DFE 的每DFE 偏移测量和消除","authors":"Yong-Un Jeong;Joo-Hyung Chae","doi":"10.1109/TIM.2024.3488135","DOIUrl":null,"url":null,"abstract":"To achieve a high input and output (I/O) bandwidth, memory interfaces adopt a parallel I/O structure, in which the offset caused by systemic and random mismatches can limit the I/O bandwidth; thus, offset measurement and correction are required. A receiver with a loop-unrolled decision feedback equalizer (DFE) can have a per-DFE offset between two loop-unrolled data paths, degrading the overall performance. We propose an offset calibration method that can identify and adjust the per-DFE offset, thereby correcting each input-referred offset between multiple lanes. We implemented a prototype that has a two-lane receiver adopting a one-tap weighted-VREF-based DFE in a 28-nm CMOS process. Its energy efficiency and area are 0.21 pJ/bit/lane and 0.004 mm2/lane, respectively. Through the offset calibration with the DFE, a bit error rate (BER) of 10-12 and an improved eye shmoo were achieved at 12 Gb/s in a total of six data lanes in three chips.","PeriodicalId":13341,"journal":{"name":"IEEE Transactions on Instrumentation and Measurement","volume":"73 ","pages":"1-8"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces\",\"authors\":\"Yong-Un Jeong;Joo-Hyung Chae\",\"doi\":\"10.1109/TIM.2024.3488135\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To achieve a high input and output (I/O) bandwidth, memory interfaces adopt a parallel I/O structure, in which the offset caused by systemic and random mismatches can limit the I/O bandwidth; thus, offset measurement and correction are required. A receiver with a loop-unrolled decision feedback equalizer (DFE) can have a per-DFE offset between two loop-unrolled data paths, degrading the overall performance. We propose an offset calibration method that can identify and adjust the per-DFE offset, thereby correcting each input-referred offset between multiple lanes. We implemented a prototype that has a two-lane receiver adopting a one-tap weighted-VREF-based DFE in a 28-nm CMOS process. Its energy efficiency and area are 0.21 pJ/bit/lane and 0.004 mm2/lane, respectively. Through the offset calibration with the DFE, a bit error rate (BER) of 10-12 and an improved eye shmoo were achieved at 12 Gb/s in a total of six data lanes in three chips.\",\"PeriodicalId\":13341,\"journal\":{\"name\":\"IEEE Transactions on Instrumentation and Measurement\",\"volume\":\"73 \",\"pages\":\"1-8\"},\"PeriodicalIF\":5.6000,\"publicationDate\":\"2024-10-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Instrumentation and Measurement\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10739359/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Instrumentation and Measurement","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10739359/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces
To achieve a high input and output (I/O) bandwidth, memory interfaces adopt a parallel I/O structure, in which the offset caused by systemic and random mismatches can limit the I/O bandwidth; thus, offset measurement and correction are required. A receiver with a loop-unrolled decision feedback equalizer (DFE) can have a per-DFE offset between two loop-unrolled data paths, degrading the overall performance. We propose an offset calibration method that can identify and adjust the per-DFE offset, thereby correcting each input-referred offset between multiple lanes. We implemented a prototype that has a two-lane receiver adopting a one-tap weighted-VREF-based DFE in a 28-nm CMOS process. Its energy efficiency and area are 0.21 pJ/bit/lane and 0.004 mm2/lane, respectively. Through the offset calibration with the DFE, a bit error rate (BER) of 10-12 and an improved eye shmoo were achieved at 12 Gb/s in a total of six data lanes in three chips.
期刊介绍:
Papers are sought that address innovative solutions to the development and use of electrical and electronic instruments and equipment to measure, monitor and/or record physical phenomena for the purpose of advancing measurement science, methods, functionality and applications. The scope of these papers may encompass: (1) theory, methodology, and practice of measurement; (2) design, development and evaluation of instrumentation and measurement systems and components used in generating, acquiring, conditioning and processing signals; (3) analysis, representation, display, and preservation of the information obtained from a set of measurements; and (4) scientific and technical support to establishment and maintenance of technical standards in the field of Instrumentation and Measurement.