{"title":"采用电荷域带宽控制方案的 20-24-GHz 紧凑型子采样 PLL","authors":"Li Wang;Zilu Liu;Ruitao Ma;C. Patrick Yue","doi":"10.1109/JSSC.2024.3488277","DOIUrl":null,"url":null,"abstract":"This article introduces a compact 20–24-GHz integer-N dual-path sub-sampling phase-locked loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the differential configuration of the type-I path, a charge-neutralization-based switched-capacitor gain control circuit is proposed to effectively optimize the phase-locked loop (PLL) loop bandwidth. Different from conventional approaches that use slope-controlled circuits or charge pumps, the proposed method achieves a wide control range with minimal in-band phase noise (PN) contribution. Rigorous analysis is introduced to accurately predict the frequency response and noise contribution of the proposed topology. The proportional-integral dual-path (DP) architecture, combined with an inductor-less true single-phase clock (TSPC) divider in the feedback path, enables a compact implementation. Fabricated using a 40-nm CMOS process, the prototype demonstrates an integrated jitter of 61.23 fs at 22 GHz from 1 kHz to 100 MHz, accompanied by a figure of merit (FoM) of −253.0 dB and a small core area of 0.057 mm2. The measurement results validate the effectiveness of the proposed gain and bandwidth control scheme.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 3","pages":"768-784"},"PeriodicalIF":4.6000,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme\",\"authors\":\"Li Wang;Zilu Liu;Ruitao Ma;C. Patrick Yue\",\"doi\":\"10.1109/JSSC.2024.3488277\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article introduces a compact 20–24-GHz integer-N dual-path sub-sampling phase-locked loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the differential configuration of the type-I path, a charge-neutralization-based switched-capacitor gain control circuit is proposed to effectively optimize the phase-locked loop (PLL) loop bandwidth. Different from conventional approaches that use slope-controlled circuits or charge pumps, the proposed method achieves a wide control range with minimal in-band phase noise (PN) contribution. Rigorous analysis is introduced to accurately predict the frequency response and noise contribution of the proposed topology. The proportional-integral dual-path (DP) architecture, combined with an inductor-less true single-phase clock (TSPC) divider in the feedback path, enables a compact implementation. Fabricated using a 40-nm CMOS process, the prototype demonstrates an integrated jitter of 61.23 fs at 22 GHz from 1 kHz to 100 MHz, accompanied by a figure of merit (FoM) of −253.0 dB and a small core area of 0.057 mm2. The measurement results validate the effectiveness of the proposed gain and bandwidth control scheme.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"60 3\",\"pages\":\"768-784\"},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10746381/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10746381/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme
This article introduces a compact 20–24-GHz integer-N dual-path sub-sampling phase-locked loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the differential configuration of the type-I path, a charge-neutralization-based switched-capacitor gain control circuit is proposed to effectively optimize the phase-locked loop (PLL) loop bandwidth. Different from conventional approaches that use slope-controlled circuits or charge pumps, the proposed method achieves a wide control range with minimal in-band phase noise (PN) contribution. Rigorous analysis is introduced to accurately predict the frequency response and noise contribution of the proposed topology. The proportional-integral dual-path (DP) architecture, combined with an inductor-less true single-phase clock (TSPC) divider in the feedback path, enables a compact implementation. Fabricated using a 40-nm CMOS process, the prototype demonstrates an integrated jitter of 61.23 fs at 22 GHz from 1 kHz to 100 MHz, accompanied by a figure of merit (FoM) of −253.0 dB and a small core area of 0.057 mm2. The measurement results validate the effectiveness of the proposed gain and bandwidth control scheme.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.