Zhaole Chu;Peiquan Jin;Yongping Luo;Xiaoliang Wang;Shouhong Wan
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引用次数: 0
摘要
与 DRAM 相比,非易失性内存(NVM)的带宽更低,延迟更高,因此存在更严重的非均匀内存访问(NUMA)效应。虽然有许多工作旨在优化 NVM 索引,但只有少数工作试图解决 NUMA 影响问题。现有方法主要依赖于本地 NVM 写缓冲区或基于 DRAM 的读缓冲区来减轻远程 NVM 访问的成本,这就带来了内存开销,并导致查找和扫描操作的性能下降。在本文中,我们介绍了一种新的 NUMA 优化持久树索引 NOBtree。NOBtree 的新颖之处有两方面。首先,NOBtree 提供了按 NUMA 复制和高效的节点迁移机制,以减少远程 NVM 访问。其次,NOBtree 提出了一种 NUMA 感知 NVM 分配器,以提高插入性能和可扩展性。我们在六个工作负载上进行了实验,以评估 NOBtree 的性能。结果表明,NOBtree 可以有效减少远程 NVM 访问次数。此外,NOBtree 的吞吐量和延迟分别比 TLBtree、Fast&Fair、ROART 和 PACtree 等现有持久性索引高出 3.23 倍和 4.07 倍。
NOBtree: A NUMA-Optimized Tree Index for Nonvolatile Memory
Nonvolatile memory (NVM) suffers from more serious nonuniform memory access (NUMA) effects than DRAM because of the lower bandwidth and higher latency. While numerous works have aimed at optimizing NVM indexes, only a few of them tried to address the NUMA impact. Existing approaches mainly rely on local NVM write buffers or DRAM-based read buffers to mitigate the cost of remote NVM access, which introduces memory overhead and causes performance degradation for lookup and scan operations. In this article, we present NOBtree, a new NUMA-optimized persistent tree index. The novelty of NOBtree is two-fold. First, NOBtree presents per-NUMA replication and an efficient node-migration mechanism to reduce remote NVM access. Second, NOBtree proposes a NUMA-aware NVM allocator to improve the insert performance and scalability. We conducted experiments on six workloads to evaluate the performance of NOBtree. The results show that NOBtree can effectively reduce the number of remote NVM accesses. Moreover, NOBtree outperforms existing persistent indexes, including TLBtree, Fast&Fair, ROART, and PACtree, by up to
$3.23\times $
in throughput and
$4.07\times $
in latency.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.