MaskedHLS:针对特定领域的屏蔽密码设计高层合成

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Nilotpola Sarma;Anuj Singh Thakur;Chandan Karfa
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引用次数: 0

摘要

如何设计和综合屏蔽加密硬件实现,使其在出现故障时能够安全地抵御电源侧信道攻击(PSCAs),是一项极具挑战性的任务。高级综合(HLS)是一种很有前途的技术,可直接从屏蔽软件生成屏蔽硬件,为探索设计空间提供了机会。然而,传统的 HLS 工具会通过屏蔽进行修改,从而改变对 PSCA 安全性的保证,导致不安全的寄存器传输层 (RTL)。此外,现有的 HLS 工具无法在指定位置放置寄存器,也无法在屏蔽加密设计中平衡并行路径。这对于阻止可能妨碍 PSCA 安全性的传播故障非常必要。本文介绍了一种针对特定领域的 HLS 工具,可直接从屏蔽软件实现中获取 PSCA 安全屏蔽硬件实现。该工具将寄存器放置在抗故障屏蔽小工具所需的特定位置,从而获得安全的 RTL。此外,它还能自动平衡并行路径,并在保持屏蔽所保证的 PSCA 安全性的同时,减少延迟。用 PRESENT 密码的 S-box 和 AES Canright 的 S-box 加上四种最先进的屏蔽小工具进行的实验结果表明,与手动插入寄存器相比,MaskedHLS 生成的 RTL 平均减少了 73.9% 的寄存器,减少了 45.7% 的延迟。通过 TVLA 测试,还显示了 MaskedHLS 生成的 RTL 的 PSCA 安全性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
The design and synthesis of masked cryptographic hardware implementations that are secure against power side-channel attacks (PSCAs) in the presence of glitches is a challenging task. High-level synthesis (HLS) is a promising technique for generating masked hardware directly from masked software, offering opportunities for design space exploration. However, conventional HLS tools make modifications that alter the guarantee against PSCA security via masking, resulting in an insecure register transfer level (RTL). Moreover, existing HLS tools cannot place registers at designated places and balance parallel paths in a masked cryptographic design. This is necessary to stop the propagation glitches that may hamper PSCA-security. This article introduces a domain-specific HLS tool tailored to obtain a PSCA secure masked hardware implementation directly from a masked software implementation. This tool places registers at specific locations required by the glitch-robust masking gadgets, resulting in a secure RTL. Furthermore, it automatically balances parallel paths and facilitates a reduction in latency while preserving the PSCA security guaranteed by masking. Experimental results with the PRESENT Cipher’s S-box and AES Canright’s S-box masked with four state-of-the-art gadgets, show that MaskedHLS produces RTLs with 73.9% decrease in registers and 45.7% decrease in latency on an average compared to manual register insertions. The PSCA security of MaskedHLS generated RTLs is also shown with TVLA test.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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