NOVELLA:用于优化片外内存能耗的非易失性末级高速缓存旁路

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Aritra Bagchi;Ohm Rishabh;Preeti Ranjan Panda
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引用次数: 0

摘要

当代多处理器片上系统(MPSoC)继续面临与能源有关的挑战,这些挑战主要来自片外数据移动。非易失性存储器(NVM)具有存储密度高、泄漏率低的特点,是一种很有前途的解决方案,但其写入速度慢、成本高。来自上一级高速缓存的回写和来自片外内存的响应会对共享的非易失性末级高速缓存(LLC)造成严重争用,从而影响系统性能,增加关键读取的排队时间。以前的研究主要通过绕过非易失性存储器写入来缓解竞争,从而解决性能问题。然而,作为系统能耗最关键组成部分之一的片外内存能耗,仍是最先进的旁路策略无法解决的问题。虽然泄漏和刷新等某些能源成分取决于系统性能,但性能优化旁路策略可能无法确保能源效率。仅以提高性能为目的的激进旁路决策可能会降低高速缓存的重用率,从而导致芯片外动态能耗的增加,并可能超过泄漏和刷新能耗的降低。虽然性能和片外内存能耗都会受到高速缓存争用和重用的影响,但实现最佳性能与最佳能耗的权衡却有所不同。我们引入了用于优化片外内存能耗的非易失性末级高速缓存旁路(NOVELLA),这是一种针对非易失性 LLC 的新型旁路策略,通过利用高速缓存争用和重用之间的权衡来优化片外内存能耗,从而实现能耗不同组成部分之间的平衡。与简单的无旁路基线相比,最先进的重用感知旁路解决方案最多可减少 8% 的片外内存能耗,竞争和重用感知旁路基线可减少 12%,而 NOVELLA 在各种 SPEC 工作负载中实现了 21% 的显著节能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy
Contemporary multiprocessor systems-on-chips (MPSoCs) continue to confront energy-related challenges, primarily originating from off-chip data movements. Nonvolatile memories (NVMs) emerge as a promising solution with their high-storage density and low leakage, yet they suffer from slow and expensive write operations. Writebacks from higher-level caches and responses from off-chip memory create significant contention at the shared nonvolatile last-level cache (LLC), affecting system performance with increased queuing for critical reads. Previous research primarily addresses the performance issues by trying to mitigate contention through the bypassing of NVM writes. Nevertheless, off-chip memory energy, one of the most critical components of system energy, remains unaddressed by state-of-the-art bypass policies. While certain energy components, such as leakage and refresh, depend on system performance, performance-optimizing bypass policies may not ensure energy efficiency. Aggressive bypass decisions aimed only at performance enhancement could degrade cache reuse, potentially outweighing reductions in leakage and refresh energies with the increase in off-chip dynamic energy. While both performance and off-chip memory energy are influenced by both cache contention and reuse, the tradeoffs for achieving optimal performance versus optimal energy are different. We introduce nonvolatile last-level cache bypass for optimizing off-chip memory energy (NOVELLA), a novel bypass policy for the nonvolatile LLC, to optimize off-chip memory energy by exploiting tradeoffs between cache contention and reuse, achieving a balance across different components of the energy. Compared to a naïve no-bypass baseline, while state-of-the-art reuse-aware bypass solutions reduce off-chip memory energy consumption by up to 8%, and a contention- and reuse-aware bypass baseline by 12%, NOVELLA achieves significant energy savings of 21% across diverse SPEC workloads.
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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