表面光电压可预测 GaP/PEDOT:PSS 和 GaP/CuSCN 异质结太阳能电池的开路电压†。

Anna C. Kundmann, Kathleen Becker and Frank E. Osterloh
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引用次数: 0

摘要

低成本、高效益地制造无机光伏(PV)器件对于在全球范围内应用这些器件非常重要。喷涂、旋涂和电沉积等溶液加工技术可以降低成本,但需要更好地了解由此产生的半导体异质结的电荷转移特性,以尽量减少界面上的光电压损失。在这项工作中,我们通过在 GaP 晶圆上旋涂 PEDOT:PSS 和电沉积 CuSCN 作为空穴传输层 (HTL) 来生成溶液处理异质结。在添加银漆作为前触点后,我们获得了短路电流密度分别为 0.40 mA cm-2 和 0.18 mA cm-2 的器件,开路电压分别为 0.47 V 和 0.43 V,PEDOT:PSS 和 CuSCN HTL 的功率转换效率分别为 0.045% 和 0.031%。表面光电压光谱(SPS)被用来研究被照亮的 GaP 接口的光化学电荷分离。通过与开路电位数据进行比较,我们发现表面光电压信号可以很好地预测器件的光电压。SPS 还显示 HTL 改进了空穴收集,并在 In/GaP 背面接触处形成了有害的肖特基结,电学测量中的 S 型电流-电压曲线进一步证明了这一点。降低肖特基势垒高度对提高器件性能至关重要。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Surface photovoltage predicts open circuit voltage in GaP/PEDOT:PSS and GaP/CuSCN heterojunction solar cells†

Surface photovoltage predicts open circuit voltage in GaP/PEDOT:PSS and GaP/CuSCN heterojunction solar cells†

The cost-effective fabrication of inorganic photovoltaic (PV) devices is important for their implementation on a global scale. Solution processing techniques, such as spray coating, spin coating, and electrodeposition, can drive down costs; however, a better understanding of the charge transfer characteristics of the resulting semiconductor heterojunctions is needed to minimize photovoltage losses at interfaces. In this work, we generate solution-processed heterojunctions by spin coating PEDOT:PSS and electrodepositing CuSCN as hole transport layers (HTLs) onto GaP wafers. After adding silver paint as a front contact, we obtain devices with short circuit current densities of 0.40 mA cm−2 and 0.18 mA cm−2, open circuit voltages of 0.47 V and 0.43 V, and power conversion efficiencies of 0.045% and 0.031% for PEDOT:PSS and CuSCN HTLs, respectively. Surface photovoltage spectroscopy (SPS) is used to study photochemical charge separation at the illuminated GaP interfaces. We find that the surface photovoltage signal is a good predictor of the photovoltage of the devices, as confirmed by comparison with open circuit potential data. SPS also reveals improved hole collection by the HTLs and a detrimental Schottky junction at the In/GaP back contact, further evidenced by S-shaped current–voltage profiles in electric measurements. Reducing the Schottky barrier height will be essential to improve device performance.

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