Effects of random ferroelectric and dielectric phase distributions on junctionless ferroelectric field effect transistors

In this study, we comprehensively investigated the effects of random ferroelectric (FE) and dielectric (DE) phase distributions on junctionless ferroelectric field-effect transistors (JL-FeFETs). The Poisson–Voronoi tessellation (PVT) algorithm, which corresponds to the physical growth mechanism, was used to obtain grain nucleation in the ferroelectric layer. The simulation results demonstrated that as the probability of FE phase decreased from 80% to 40%, the standard deviation of the memory window (${\sigma }_{\text{MW}}$) increased from 62.4 to 99.5 mV, and the possibility of forming a blocking current path from the source to the drain increased, which degraded the memory window (MW). The simulation results indicated that decreasing the gate length and width increased device variations. Furthermore, ${\sigma }_{\text{MW}}$ decreased from 84.5 to 58.9 mV as the grain size decreased from 5 to 3 nm.