A column bus self-acceleration circuit for large array CMOS image sensor

This paper presents a column bus self-acceleration circuit based on dynamically regulating bias current, which aims to reduce the settling time of pixel output signal caused by the parasitic effect of the column bus. Through the mathematical model of the column bus, the relationship between the settling time and the bias current is analyzed. The proposed circuit is designed by a 110 nm CMOS process. Under the condition with a parasitic capacitance of 10.61 pF and a parasitic resistance of 6.3 kΩ, simulation results show that the proposed self-acceleration circuit can reduce the settling time of pixel output signal from 13.8μs to 4.1μs. Compared with the traditional column bus structure, the settling time of the pixel output signal is reduced by 71 %. The self-acceleration circuit can effectively improve the readout speed of large array CMOS image sensor.