A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability

This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61$\times$/1.33$\times$/1.44$\times$/1.63$\times$/1.46$\times$, and reduction in power consumption during read operation by 1.02$\times$/1.55$\times$/ 1.01$\times$/1.81$\times$/1.97$\times$ in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67$\times$/1.71$\times$/2.59$\times$/1.45$\times$/1.97$\times$, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03$\times$/1.01$\times$/1.65$\times$/1.54$\times$/1.43$\times$, and 1.42$\times$/1.33$\times$/1.41$\times$/1.02$\times$/1.62$\times$, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.