A Hardware-Efficient Novelty-Aware Spike Sorting Approach for Brain-Implantable Microsystems.

Unsupervised spike sorting, a vital processing step in real-time brain-implantable microsystems, is faced with the prominent challenge of managing nonstationarity in neural signals. In long-term recordings, spike waveforms gradually change and new source neurons are likely to become activated. Adaptive spike sorters combined with on-implant training units effectively process the nonstationary signals at the cost of high hardware resource utilization. On the other hand, static approaches, while being hardware-friendly, are subjected to decreased processing performance in such recordings where the neural signal characteristics gradually change. To strike a balance between the hardware cost and processing performance, this study proposes a hardware-efficient novelty-aware spike sorting approach that is capable of dealing with both variated spike waveforms and spike waveforms generated from new source neurons. Its improved hardware efficiency compared to adaptive ones and capability of dealing with nonstationary signals make it attractive for implantable applications. The proposed novelty-aware spike sorting especially would be a good fit for brain-computer interfaces where long-term, real-time interaction with the brain is required, and the available on-implant hardware resources are limited. Our unsupervised spike sorting benefits from a novelty detection process to deal with neural signal variations. It tracks the spike features so that in case of detecting an unexpected change (novelty detection) both on and off-implant parameters are updated to preserve the performance in new state. To make the proposed approach agile enough to be suitable for brain implants, the on-implant computations are reduced while the computational burden is realized off-implant. The performance of our proposed approach is evaluated using both synthetic and real datasets. The results demonstrate that, in the mean, it is capable of detecting 94.31% of novel spikes (wave-drifted or emerged spikes) with a classification accuracy (CA) of 96.31%. Moreover, an FPGA prototype of the on-implant circuit is implemented and tested. It is shown that in comparison to the OSORT algorithm, a pivotal spike sorting method, our spike sorting provides a higher CA at significantly lower hardware resources. The proposed circuit is also implemented in a 180-nm standard CMOS process, achieving a power consumption of 1.78[Formula: see text][Formula: see text] per channel and a chip area of 0.07[Formula: see text]mm² per channel.