A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry

This paper presents a signal-chain friendly 12-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS, which is optimized to achieve a 68.5 dB-SNDR, 100-MS/s sample rate with 54.5$\text{\%}$ of maximum available input range. The implemented ADC employs an improved clock booster and latch-register to achieve high on-conductance of nmos switches and low-leakage data storage. It also explores an adaptive non-overlapping complementary clock generator and a dedicated $V_{CM}$ buffer to accommodate process, voltage, and temperature (PVT) conditions. The relative variation of non-overlapping time is reduced by 50$\text{\%}$ compared to the conventional method, and the signal-to-distortion ratio (SDR) of residue amplification is improved by 8 dB . Moreover, on-chip bit weight calibration is implemented to address the gain error brought by capacitor mismatch and inner-stage gain error. The prototype ADC is simulated under 5 corners, −40 to 125 $°C$, and 1.1 V $\pm$  2.5$\text{\%}$. For a Nyquist input, the simulated SNDR under typical corner is 68.5 dB , which can remain over 66 dB under PVT conditions. The achieved Walden Figure of Merit (FoM) is 12.4-fJ/conv.-step.