探索高级合成设计空间的基于分解的分布估计算法

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yuan Yao, Huiliang Hong, Shanshan Wang, Chenglong Xiao
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引用次数: 0

摘要

由于集成电路设计的复杂性不断增加,以及对高效设计方法的需求,高层合成(HLS)得到了长足的发展。HLS 提高了设计规范的抽象水平,使设计人员能够专注于硬件功能,从而提高了生产率并减少了验证工作。然而,HLS 面临的一个关键挑战是如何有效地探索广阔的设计空间,找到帕累托最优设计。本文介绍了一种在 HLS 中进行多目标设计空间探索的新方法。我们的方法利用基于分解的多目标进化算法(MOEA/D)框架将设计空间探索问题分解为更简单的子问题,并利用分布估计算法(EDA)建立概率模型以生成候选解决方案,从而减少了所需的昂贵合成运行次数。实验结果表明,所提出的方法收敛速度更快,合成次数减少了 24.34% 到 32.01%,明显优于最先进的方法。我们的方法以最低的平均 ADRS 值实现了卓越的帕累托前沿,分别比 Lattice-expl、ϵ -Constraint GA 和 NSGA-II 高出 85.64%、39.90% 和 33.31%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration
High-Level Synthesis (HLS) has evolved significantly due to the increasing complexity of integrated circuit design and the demand for efficient design methodologies. HLS, which raises the abstraction level of design specification, allows designers to focus on hardware functionality, thus enhancing productivity and reducing verification efforts. However, a key challenge in HLS is efficiently exploring the vast design space to find the Pareto-optimal designs. In this paper, we introduce a novel approach for multi-objective design space exploration in HLS. Our methodology decomposes the design space exploration problem into simpler sub-problems using the Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) framework and utilizes the Estimation of Distribution Algorithm (EDA) to build a probabilistic model for generating candidate solutions, thereby reducing the required number of expensive synthesis runs. Experimental results show that the proposed method has a faster convergence speed and reduces the number of syntheses by 24.34% to 32.01%, which significantly outperforms state-of-the-art works. Our approach achieves superior Pareto fronts with the lowest average ADRS value, outperforming Lattice-expl, ϵ -Constraint GA, and NSGA-II by 85.64%, 39.90%, and 33.31% respectively.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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