A wideband high-PSR OCL LDO using a gain-relaxed OTA featuring dynamic complex zeros frequency compensation

This article proposes an Output-Capacitor-Less (OCL) Low-Dropout (LDO) regulator with an assisted positive feedback loop technique, which mimics a negative resistance, along with a single common-gate stage. Conventional techniques utilize multistage high-gain OTA to achieve a high DC loop gain. However, such an OTA suffers from high power consumption and sophisticated frequency compensation mechanisms. Instead, the use of a single-stage relatively low-gain OTA helps to extend the bandwidth. Then, the overall DC loop gain is maximized by the proposal of a novel negative resistance circuit. To further improve the PSR, a bulk-driven ripple canceling path that is insensitive to process corners is proposed making the LDO suitable for high-PSR applications. Stability is another challenge in the design of OCL LDOs due to its associated complex poles. We propose a new frequency compensation technique by introducing two complex zeros to eliminate these complex poles. Hence, the overall stability is improved. Since these complex poles location vary from light to heavy loads, the proposed zeros dynamically change accordingly. Besides, this suggested mechanism has been analyzed using the generalized time-and-transfer constants (TTCs) circuit analysis technique. Under heavy load conditions, the suggested LDO has attained phase and gain margins of 62.8° and 29 dB, respectively. Moreover, Monte Carlo simulations along with process and temperature variations have been investigated to prove the reliability of such a frequency compensation technique. The proposed LDO has been implemented in 65 nm CMOS technology node with a short pass transistor length of $100\mathrm{nm}$. The simulation results reveals that the LDO draws $299.4\mu A$ of quiescent current under light load conditions and $296.8\mu A$ under heavy load conditions (including the bandgap voltage reference). The suggested LDO functions at $1.2V$ supply voltage, delivers $0.93V$ output voltage and can handle a load current up to $10\mathrm{mA}$ with load regulation of $17\mu \mathrm{V/mA}$, line regulation of $2.22\mathrm{mV/V}$, and PSR of $-48.7\mathrm{dB}$ at low frequencies. The PSR at $1\mathrm{MHz}$ is at least $-32.5\mathrm{dB}$ which is superior to the reported recent LDOs.