An 11-bit low power column-parallel single slope ADC with comparator toggle prediction technique for CMOS image sensor

This paper proposes an 11-bit low power column-parallel SS ADC with DCDS for CMOS image sensors. The proposed SS ADC reduces the power consumption in three ways. Firstly, using a combination of coarse and fine quantization can reduce power consumption of counter. Secondly, changing the operation state can remove the bit width inverter. Thirdly, the comparator power is reduced by making each column of comparators switch off after the end of the comparison function. The proposed ADC is fabricated in a 110 nm 1P4M CMOS technology and has a DNL of +0.64/−0.54 LSB and an INL of +0.04/−6.7 LSB at a sampling frequency of 29.9 kS/s. The single column SS ADC has the power consumption ranging from 39.6 μW to 74.87 μW. Compared with the conventional SS ADC, the minimum and the maximum reduction of the power consumption are 20.1 % and 43.8 %, respectively. The average power saving is 34.5 %.