Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process

As integrated circuit technology continues to shrink, single-event multiple-node-upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE) that can achieve single-node-upset self-recovery. Besides, a quadruple-modular redundancy fault-tolerant mechanism is constructed. The 4DICE-C uses the clocked quadruple-input C-element at the output stage, the 4DICE-V uses clocked voter at the output stage. Compared with previous hardened latches containing C-elements, the 4DICE-V is less sensitive to high impedance state and can efficiently tolerate soft errors at internal nodes. In addition, compared with previous single-event triple-node-upset and quadruple-node-upset hardened latches, the 4DICE-C latch has achieved 100 % tolerance efficiency of single-event quadruple-node-upset, the best delay overhead and APDP comprehensive overhead, 18.69 % lower than average delay.