Fault-tolerant routing for reliable packet transmission in on-chip networks

In deep submicron technology, integrated circuits are susceptible to various factors, leading to increased probabilities of chip failures. The routers within NoC, connecting processor cores, also experience elevated fault rates, thereby impacting normal communication between processors. Therefore, implementing fault-tolerant mechanisms in on-chip networks becomes particularly crucial. In this paper, we propose a fault-tolerant routing scheme to ensure the accurate transmission, injection, and ejection of packets, even in the event of router failures at any node in the NoC. We have enhanced the router architecture by integrating bypass controllers (BCs) to connect east–west and north–south links, and linking these BCs to the local. This modification enables uninterrupted communication between cores. Based on this architecture, we propose a straightforward routing algorithm aimed at minimizing detours and ensuring packet transmission along the shortest path , thus reducing transmission latency. Experimental results demonstrate that our proposed fault-tolerant scheme significantly enhances reliability under scenarios involving multiple faulty routers when compared to existing schemes.