采用 CSCR 优先拓扑结构的单片式 12.7 W/mm2、峰值效率 92% 开关电容器 DC-DC 转换器

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Nicolas Butzen;Harish K. Krishnamurthy;Jingshu Yu;Zakir K. Ahmed;Sheldon Weng;Krishnan Ravichandran;Ramez Hosseinian Ahangharnejhad;James Waldemer;Christopher Pelto;James W. Tschanz
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引用次数: 0

摘要

本文介绍了用于单片式开关电容稳压器(SCVR)的连续可扩展转换比率(CSCR)第一拓扑结构,大大提高了 CSCR SCVR 在更高输入电压下的性能。该拓扑结构将固定比率 2:1 级与 CSCR 级结合在一起,限制了 CSCR 级上的电压,同时提高了允许输入电压,而无需依赖堆叠电容器或晶体管。此外,通过使固定比级和 CSCR 级缺相运行,CSCR 的中间轨和开关的效率提高了一倍,从而减少了所需晶体管的占用空间。本文讨论了这项技术的可扩展实施方案,该方案利用可阵列的电压调节器(VR)内核,其中包括所需的功率晶体管、电容器以及本地信号生成电路,然后将其与单个集中式控制器相结合,以满足小型和大型功率域的电流需求。该 VR 采用高密度金属-绝缘体-金属 (MIM) 电容器在英特尔 16 技术上实现,其测量结果表明了所建议方法的瞬态性能和可靠性,同时还展示了单片式电压转换创纪录的 12.7 W/mm2 峰值功率密度和 92% 的峰值效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Monolithic 12.7 W/mm2, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology
This article introduces the continuously scalable conversion-ratio (CSCR)-first topology for monolithic switched-capacitor voltage regulators (SCVRs), substantially improving the performance of CSCR SCVRs for higher input voltages. The topology combines fixed-ratio 2:1 stages together with a CSCR stage to limit the voltage across the CSCR stage while boosting the allowable input voltage higher without relying on stacking capacitors or transistors. Furthermore, by running the fixed-ratio and CSCR stage out of phase, the effectiveness of the CSCR’s intermediate rails and switches is doubled, thus reducing the required transistor footprint. This article discusses a scalable implementation of this technology, leveraging an array-able voltage regulator (VR) core that encompasses the required powertransistors, capacitors, as well as local signal generation circuits, that is then combined with a single centralized controller to meet the current demands of small and large power domains. Measurement results of the VR, realized on Intel 16 technology using high-density metal-insulator-metal (MIM) capacitors, demonstrate the transient performance and reliability of the proposed approach, while showcasing a record 12.7 W/mm2 peak power density for monolithic voltage conversion, and 92% peak efficiency.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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