Nicolas Butzen;Harish K. Krishnamurthy;Jingshu Yu;Zakir K. Ahmed;Sheldon Weng;Krishnan Ravichandran;Ramez Hosseinian Ahangharnejhad;James Waldemer;Christopher Pelto;James W. Tschanz
{"title":"采用 CSCR 优先拓扑结构的单片式 12.7 W/mm2、峰值效率 92% 开关电容器 DC-DC 转换器","authors":"Nicolas Butzen;Harish K. Krishnamurthy;Jingshu Yu;Zakir K. Ahmed;Sheldon Weng;Krishnan Ravichandran;Ramez Hosseinian Ahangharnejhad;James Waldemer;Christopher Pelto;James W. Tschanz","doi":"10.1109/JSSC.2024.3465388","DOIUrl":null,"url":null,"abstract":"This article introduces the continuously scalable conversion-ratio (CSCR)-first topology for monolithic switched-capacitor voltage regulators (SCVRs), substantially improving the performance of CSCR SCVRs for higher input voltages. The topology combines fixed-ratio 2:1 stages together with a CSCR stage to limit the voltage across the CSCR stage while boosting the allowable input voltage higher without relying on stacking capacitors or transistors. Furthermore, by running the fixed-ratio and CSCR stage out of phase, the effectiveness of the CSCR’s intermediate rails and switches is doubled, thus reducing the required transistor footprint. This article discusses a scalable implementation of this technology, leveraging an array-able voltage regulator (VR) core that encompasses the required powertransistors, capacitors, as well as local signal generation circuits, that is then combined with a single centralized controller to meet the current demands of small and large power domains. Measurement results of the VR, realized on Intel 16 technology using high-density metal-insulator-metal (MIM) capacitors, demonstrate the transient performance and reliability of the proposed approach, while showcasing a record 12.7 W/mm2 peak power density for monolithic voltage conversion, and 92% peak efficiency.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"4114-4123"},"PeriodicalIF":4.6000,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Monolithic 12.7 W/mm2, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology\",\"authors\":\"Nicolas Butzen;Harish K. Krishnamurthy;Jingshu Yu;Zakir K. Ahmed;Sheldon Weng;Krishnan Ravichandran;Ramez Hosseinian Ahangharnejhad;James Waldemer;Christopher Pelto;James W. Tschanz\",\"doi\":\"10.1109/JSSC.2024.3465388\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article introduces the continuously scalable conversion-ratio (CSCR)-first topology for monolithic switched-capacitor voltage regulators (SCVRs), substantially improving the performance of CSCR SCVRs for higher input voltages. The topology combines fixed-ratio 2:1 stages together with a CSCR stage to limit the voltage across the CSCR stage while boosting the allowable input voltage higher without relying on stacking capacitors or transistors. Furthermore, by running the fixed-ratio and CSCR stage out of phase, the effectiveness of the CSCR’s intermediate rails and switches is doubled, thus reducing the required transistor footprint. This article discusses a scalable implementation of this technology, leveraging an array-able voltage regulator (VR) core that encompasses the required powertransistors, capacitors, as well as local signal generation circuits, that is then combined with a single centralized controller to meet the current demands of small and large power domains. Measurement results of the VR, realized on Intel 16 technology using high-density metal-insulator-metal (MIM) capacitors, demonstrate the transient performance and reliability of the proposed approach, while showcasing a record 12.7 W/mm2 peak power density for monolithic voltage conversion, and 92% peak efficiency.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"59 12\",\"pages\":\"4114-4123\"},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10706589/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10706589/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Monolithic 12.7 W/mm2, 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology
This article introduces the continuously scalable conversion-ratio (CSCR)-first topology for monolithic switched-capacitor voltage regulators (SCVRs), substantially improving the performance of CSCR SCVRs for higher input voltages. The topology combines fixed-ratio 2:1 stages together with a CSCR stage to limit the voltage across the CSCR stage while boosting the allowable input voltage higher without relying on stacking capacitors or transistors. Furthermore, by running the fixed-ratio and CSCR stage out of phase, the effectiveness of the CSCR’s intermediate rails and switches is doubled, thus reducing the required transistor footprint. This article discusses a scalable implementation of this technology, leveraging an array-able voltage regulator (VR) core that encompasses the required powertransistors, capacitors, as well as local signal generation circuits, that is then combined with a single centralized controller to meet the current demands of small and large power domains. Measurement results of the VR, realized on Intel 16 technology using high-density metal-insulator-metal (MIM) capacitors, demonstrate the transient performance and reliability of the proposed approach, while showcasing a record 12.7 W/mm2 peak power density for monolithic voltage conversion, and 92% peak efficiency.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.