Assessment of Trap Charges for Analog/RF FOMs and Linearity Behaviour on InAs Based Dual Metal Hetero Gate Oxide TFET for Enhanced Reliability

The aim of this study is to examine a low-power, InAs/Si hetero-gate oxide double-gate Tunnel field effect transistor (H-DM-DG-InAs-TFET) for high frequency application and to determine how trap charges (ITCs) affect the DC characteristics and analog/RF electrical performance metrics of the device. It is unfeasible to disregard the trap charges because the device's performance and reliability are negatively impacted by the buildup of trap charges at the interface between the semiconductor and oxide. Hence, an in-depth analysis of the performance characteristics of the proposed device, a InAs/Si hetero-gate oxide double-gate Tunnel FET (H-DM-DG-InAs-TFET), is conducted in this work to ascertain the impact of interface trap charges (ITCs). Comparison study of proposed device with dual metal gate Si Tunnel Field Effect Transistor (DM-DG-Si-TFET) is conducted. The proposed device is capable of effortlessly carrying enhanced ON current (1.54 × 10^–3 A/µm) and exhibits improved current ratio (1.63 × 10¹¹). To ascertain the device's suitability for low-power applications, its threshold voltage is determined by employing a constant current methodology. An improvement in threshold voltage (0.17 V) is noted. According to the study, the efficacy of the proposed device was enhanced due to the dielectric engineering performed on the oxide layer. Further investigation is conducted into the impact of ITCs on linearity parameters, as advanced communication device necessitates linear responses. The comparison with the DM-DG-Si-TFET reveals that the proposed TFET has virtually no distortion and a negligible impact on the linearity metrics. This indicates that the proposed TFET can be utilised in extremely low-power, high-frequency electrical devices.