Experimental investigation and performance evaluation of an asymmetrical Eleven-Level Multilevel Inverter (ELMLI) with reduced switching count and voltage stress

In this study an eleven-level multilevel inverter (ELMLI) with reduced switching requirements and lower voltage stress is introduced. The architecture comprises of eight semiconductor devices and only one capacitor, yielding a voltage boosting output of 1.67. Gate pulses for the inverter circuit are provided through a straight forward nearest level control (NLC) method. To highlight the superiority of this topology, a assessment is conducted with recent designs concerning the numbers of semiconductor devices, diodes, sources, and capacitors employed. The Total Harmonic Distortion (THD) is measured at 7.61%, which nearly meets acceptable limits. Subsequently, the suggested circuit is simulated operationally and functionally using software tools such as PLECS and MATLAB (SIMULINK). Experimental validation is also carried out under various loading conditions using the setup.