A novel nanoscale FD-SOI MOSFET with energy barrier and heat-sink engineering for enhanced electric field uniformity

This paper aims to present a novel method to mitigate the undesirable issues associated with short-channel-effects (SCEs) and the critical lattice temperature of a fully depleted silicon-on-insulator (FD-SOI) MOSFET in the nanoscale regime. The proposed approach is based on simultaneously merging the energy barrier and heat-sink engineering simultaneously. Hafnium oxide as a high-k dielectric inside the channel region around the drain region is embedded to redistribute the band energy resulting in the enhancement of the energy barrier. This reformation of the band profile reduces variations in the channel depletion charge volume percentage caused by the drain voltage, thereby mitigating short-channel effects (SCEs). In order to promote effective thermal conduction, a portion of the buried oxide is replaced by doped P-type silicon which acts as an effective heat-sink. The devices under the investigation have been simulated using SILVACO software, considering the comprehensive physical models. Drain-Induced Barrier Lowering (DIBL), leakage current, I_on to I_off ratio, subthreshold swing, hot carrier effect and lattice temperature as the essential parameters have been successfully improved for the proposed device in comparison to the conventional device.