带电荷汇合相位以降低电感器电流的 12 至 1-1.8 V 混合直流-直流转换器

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Yichao Ji;Ji Jin;Lin Cheng
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引用次数: 0

摘要

本文介绍了一种具有电荷汇聚阶段(CCP-HB)的 12 V 输入和 1-1.8 V 输出混合降压转换器。在这一阶段,来自多条路径的电荷汇聚到一个飞行电容器中,从而增加其上积累的电荷。这些电荷在另一阶段与电感器并联转移到输出端,因此,在整个电压转换率 (VCR) 范围内,电感器的平均电流始终小于负载电流的一半。这种方法大大降低了直流电阻(DCR)传导损耗,减轻了对笨重电感器的依赖。此外,输入和输出之间采用了堆叠式开关电容器网络(SCN),以降低功率开关的电压应力,从而提高效率。该转换器采用 0.18- $\mu $ m BCD 工艺制造,仅使用 5-V 和 1.8-V NMOS 作为功率开关。测量结果表明,该转换器的峰值效率达到 95.4%,DCR 较小,为 10.5 m $\Omega $。此外,CCP 能够使用与 2016 系列一样小的紧凑型电感器(2{times }1.6{times }1$ mm3),其大 DCR 为 57 m $\Omega $,低饱和电流为 3.6 A,可提供高达 5 A 的满载电流。该转换器的峰值效率仍然保持在 94.7%,总无源体积的电流密度高达 685 A/cm3。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 12-to-1–1.8-V Hybrid DC-DC Converter With a Charge Converging Phase for Inductor Current Reduction
This article presents a 12-V-input and 1–1.8-V-output hybrid buck converter featuring a charge converging phase (CCP-HB). During this phase, charges from multiple paths converge into one flying capacitor, increasing the charge accumulated on it. Such charge gets transferred to the output in parallel with the inductor during the other phase, and thus, the average inductor current is reduced to consistently less than half of the load current across the entire voltage conversion ratio (VCR) range. This approach significantly reduces dc resistance (DCR) conduction loss and mitigates the reliance on a bulky inductor. Besides, a stacked switched-capacitor network (SCN) is adopted between the input and the output to reduce voltage stress on power switches for better efficiency. The converter was fabricated in a 0.18- $\mu $ m BCD process, utilizing only 5- and 1.8-V NMOS as power switches. Measurement results show that the converter achieves a peak efficiency of 95.4% with a small DCR of 10.5 m $\Omega $ . Moreover, the CCP enables the use of a compact inductor as small as the 2016 series ( $2{\times }1.6{\times }1$ mm3) with a large DCR of 57 m $\Omega $ and a low saturation current of 3.6 A to deliver a full load of up to 5 A. The converter still maintains a peak efficiency of 94.7%, and the current density of total passive volume is up to 685 A/cm3.
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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