Jianzheng Li , Yuchen Zhao , Weimin Hu , Jinghan Yao , Ziwei Liu , Yajie Qin
{"title":"采用 NS-CAL 方法的 62.5 kHz-BW 92 dB-SNDR 噪声整形 SAR ADC","authors":"Jianzheng Li , Yuchen Zhao , Weimin Hu , Jinghan Yao , Ziwei Liu , Yajie Qin","doi":"10.1016/j.mejo.2024.106401","DOIUrl":null,"url":null,"abstract":"<div><p>DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method\",\"authors\":\"Jianzheng Li , Yuchen Zhao , Weimin Hu , Jinghan Yao , Ziwei Liu , Yajie Qin\",\"doi\":\"10.1016/j.mejo.2024.106401\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S187923912400105X\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S187923912400105X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method
DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.