M2M: 在多芯片架构上加速多个 DNN 的细粒度映射框架

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jinming Zhang;Xuyan Wang;Yaoyao Ye;Dongxu Lyu;Guojie Xiong;Ningyi Xu;Yong Lian;Guanghui He
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引用次数: 0

摘要

随着人工智能的发展,多个深度神经网络(DNN)的协作对现有的嵌入式系统和云系统至关重要,特别是在自动驾驶应用以及增强和虚拟现实(AR/VR)应用中。为了在成本和性能之间进行权衡,基于芯片组的 DNN 加速器已成为加速 DNN 工作负载的一种有前途的解决方案。然而,现有的多 DNN 映射方法大多针对单片机,无法解决新兴的多芯片架构所面临的问题,如分布式内存访问、复杂的异构互连网络和计算资源扩展等问题。在这项工作中,我们提出了在多芯片架构上加速多个 DNN 的细粒度映射框架 M2M。它包括可重构数据流加速器的时间和空间任务调度,以及异构互连网络中的通信感知任务映射。为了提高通信效率并降低整体延迟,我们进一步提出了针对包上网络(NoP)链路的微调服务质量(QoS)策略。据我们所知,这是首个针对多芯片架构上多个 DNN 的细粒度映射框架。我们使用遗传算法和模拟退火算法实现了所提出的细粒度映射框架。实验结果表明,与最先进的相关工作相比,我们的工作在视觉、语言和混合工作负载下实现了 7.18%-61.09% 的延迟降低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture
With the advancement of artificial intelligence, the collaboration of multiple deep neural networks (DNNs) has been crucial to existing embedded systems and cloud systems, especially for automatic driving applications as well as augmented and virtual reality (AR/VR) applications. To trade off between cost and performance, chiplet-based DNN accelerators have emerged as a promising solution for accelerating DNN workloads. However, most existing mapping methods for multiple DNNs target for the monolithic chip, which fail to solve the problems faced by the emerging multi-chiplet architecture, such as the problems of distributed memory access, complex heterogeneous interconnect network, and the scaling-up of computing resources. In this work, we propose M2M, a fine-grained mapping framework for accelerating multiple DNNs on a multi-chiplet architecture. It includes a temporal and spatial task scheduling for reconfigurable dataflow accelerators and a communication-aware task mapping in a heterogeneous interconnect network. To enhance communication efficiency and reduce the overall latency, we further propose a fine-tuned quality-of-service (QoS) policy for network-on-package (NoP) links. To the best of our knowledge, this is the first fine-grained mapping framework for multiple DNNs on a multi-chiplet architecture. We implemented the proposed fine-grained mapping framework using genetic algorithm and simulated annealing algorithm. Experimental results show that our work achieves 7.18%–61.09% latency reduction under vision, language, and mixed workloads when compared with the state-of-the-art related work.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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