{"title":"多内核极坐标编码的非卷积、流水线和分阶段折叠架构","authors":"Hossein Rezaei;Elham Abbasi;Nandana Rajatheva;Matti Latva-Aho","doi":"10.1109/TVLSI.2024.3436872","DOIUrl":null,"url":null,"abstract":"Over the past decade, polar codes have received significant attraction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary (\n<inline-formula> <tex-math>$2 \\times 2$ </tex-math></inline-formula>\n) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to achieve increased flexibility in code length. This article proposes unrolled and pipelined architectures for encoding both systematic and nonsystematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary (\n<inline-formula> <tex-math>$3 \\times 3$ </tex-math></inline-formula>\n), or binary-ternary mixed kernels. Furthermore, two novel nonsystematic stage-folded encoders, designed to minimize resource usage, have been introduced for the encoding of pure-ternary and MK codes. The proposed MK encoders additionally provide the functionality of dynamic kernel assignment. The proposed architectures exhibit an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide tradeoffs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially pipelined polar encoder of size \n<inline-formula> <tex-math>$N=4096$ </tex-math></inline-formula>\n operating at a frequency of 270 MHz gives a throughput of 1080 Gb/s. In addition, a new compiler scripted in Python is introduced to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes\",\"authors\":\"Hossein Rezaei;Elham Abbasi;Nandana Rajatheva;Matti Latva-Aho\",\"doi\":\"10.1109/TVLSI.2024.3436872\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Over the past decade, polar codes have received significant attraction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary (\\n<inline-formula> <tex-math>$2 \\\\times 2$ </tex-math></inline-formula>\\n) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to achieve increased flexibility in code length. This article proposes unrolled and pipelined architectures for encoding both systematic and nonsystematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary (\\n<inline-formula> <tex-math>$3 \\\\times 3$ </tex-math></inline-formula>\\n), or binary-ternary mixed kernels. Furthermore, two novel nonsystematic stage-folded encoders, designed to minimize resource usage, have been introduced for the encoding of pure-ternary and MK codes. The proposed MK encoders additionally provide the functionality of dynamic kernel assignment. The proposed architectures exhibit an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide tradeoffs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially pipelined polar encoder of size \\n<inline-formula> <tex-math>$N=4096$ </tex-math></inline-formula>\\n operating at a frequency of 270 MHz gives a throughput of 1080 Gb/s. In addition, a new compiler scripted in Python is introduced to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10636939/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10636939/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes
Over the past decade, polar codes have received significant attraction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary (
$2 \times 2$
) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to achieve increased flexibility in code length. This article proposes unrolled and pipelined architectures for encoding both systematic and nonsystematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary (
$3 \times 3$
), or binary-ternary mixed kernels. Furthermore, two novel nonsystematic stage-folded encoders, designed to minimize resource usage, have been introduced for the encoding of pure-ternary and MK codes. The proposed MK encoders additionally provide the functionality of dynamic kernel assignment. The proposed architectures exhibit an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide tradeoffs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially pipelined polar encoder of size
$N=4096$
operating at a frequency of 270 MHz gives a throughput of 1080 Gb/s. In addition, a new compiler scripted in Python is introduced to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.