多内核极坐标编码的非卷积、流水线和分阶段折叠架构

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Hossein Rezaei;Elham Abbasi;Nandana Rajatheva;Matti Latva-Aho
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引用次数: 0

摘要

在过去十年中,极地编码受到了极大的关注,并被选为第五代(5G)无线通信系统中控制信道的编码方法。然而,传统极性编码仅依赖于二进制(2 美元乘 2 美元)内核,这就限制了其块长度只能是 2 的幂次。本文提出了用于编码系统性和非系统性 MK 极码的非滚动和流水线架构,能够对二元、三元(3 美元乘以 3 美元)或二元三元混合内核构建的极码进行高吞吐量编码。此外,还引入了两种新型非系统分阶段折叠编码器,旨在最大限度地减少资源使用,用于纯三元码和 MK 码的编码。拟议的 MK 编码器还提供了动态内核分配功能。所提出的架构支持 83 种不同的编码,并提供了在吞吐量和资源消耗之间进行权衡的各种架构,从而展现出前所未有的灵活性。FPGA 实现结果表明,在 270 MHz 频率下运行的部分流水线极性编码器(大小为 $N=4096$)的吞吐量可达 1080 Gb/s。此外,还引入了一个新的 Python 编译器,用于自动生成所需的编码器 HDL 模块。通过插入所需的参数,设计人员可以简单地获得所有必要的 VHDL 文件,用于 FPGA 实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes
Over the past decade, polar codes have received significant attraction and have been selected as the coding method for the control channel in fifth-generation (5G) wireless communication systems. However, conventional polar codes are reliant solely on binary ( $2 \times 2$ ) kernels, which restricts their block length to being only powers of 2. In response, multi-kernel (MK) polar codes have been proposed as a viable solution to achieve increased flexibility in code length. This article proposes unrolled and pipelined architectures for encoding both systematic and nonsystematic MK polar codes, capable of high-throughput encoding of codes constructed with binary, ternary ( $3 \times 3$ ), or binary-ternary mixed kernels. Furthermore, two novel nonsystematic stage-folded encoders, designed to minimize resource usage, have been introduced for the encoding of pure-ternary and MK codes. The proposed MK encoders additionally provide the functionality of dynamic kernel assignment. The proposed architectures exhibit an unprecedented level of flexibility by supporting 83 different codes and offering various architectures that provide tradeoffs between throughput and resource consumption. The FPGA implementation results demonstrate that a partially pipelined polar encoder of size $N=4096$ operating at a frequency of 270 MHz gives a throughput of 1080 Gb/s. In addition, a new compiler scripted in Python is introduced to automatically generate HDL modules for the desired encoders. By inserting the desired parameters, a designer can simply obtain all the necessary VHDL files for FPGA implementation.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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