采用串音抑制和不均匀性补偿技术的电阻式触觉传感器阵列 CMOS 读出电路

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yao Li;Junfeng Geng;Mao Ye;Jiaji He;Xiaoxiao Zheng;Qiuwei Wang;Yiqiang Zhao
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引用次数: 0

摘要

本文提出了一种用于电阻式触觉传感器阵列的新型读出电路。基于二维扫描机制,提出了一种将相关双采样(CDS)与零电位法(ZPM)相结合的串扰抑制技术。同一传感器在不同偏置条件下的输出被捕获两次,并通过通道并行的全差分增益级放大,执行类似的减法。为了实现非均匀性补偿,注入读出通道的电流由通道并行数模转换器(DAC)调节。一个连续逼近寄存器(SAR)模数转换器(ADC)执行量化,芯片可以作为串行外设接口(SPI)从站来更新寄存器值,用于增益配置、功耗控制和非均匀性补偿。180nm CMOS原型芯片占地$4.8~\text {mm}^{2}$,功耗$285~\mu $ W.为了验证设计,我们构建了一个触觉传感系统,使用读出电路和$10\ × 10$的柔性传感器阵列。采用本文提出的技术,阵列传感器的读出误差小于0.3‰。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques
This article presents a novel readout circuit for the resistive tactile sensor array. Based on the 2-D scanning mechanism, a crosstalk suppression technique is proposed by combining the correlated double sampling (CDS) and zero potential method (ZPM). The output of the same sensor under different bias conditions is captured twice and amplified by a channel-parallel fully differential gain stage, performing analogous subtraction. To achieve nonuniformity compensation, the current injected into the readout channel is adjusted by the channel-parallel digital-to-analog converter (DAC). A successive approximation register (SAR) analog-to-digital converter (ADC) performs quantization, and the chip can be used as a serial peripheral interface (SPI) slave to update register values for gain configuration, power consumption control, and nonuniformity compensation. The 180-nm CMOS prototype chip occupies an area of $4.8~\text {mm}^{2}$ and consumes $285~\mu $ W. In order to validate the design, a tactile sensing system is built, using the readout circuit along with a $10\times 10$ flexible sensor array. With the techniques proposed in this article, the readout error of the sensors in array is less than 0.3‰.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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