具有并行转换功能的 800-MS/s 8.2-ENOB TDC 辅助流水线 SAR ADC

IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Shao-Yu Wang;Tai-Cheng Lee
{"title":"具有并行转换功能的 800-MS/s 8.2-ENOB TDC 辅助流水线 SAR ADC","authors":"Shao-Yu Wang;Tai-Cheng Lee","doi":"10.1109/TCSII.2024.3445653","DOIUrl":null,"url":null,"abstract":"This brief presents a ring amplifier embedded with the time-to-digital converter (TDC) to implement parallel conversion techniques in a pipelined-SAR ADC. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This technique need no additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. Fabricated in a 28-nm CMOS technology, the ADC achieves a 45.06-dB SNDR at 800 MS/s and consumes 4.84 mW with a 0.9-V supply, yielding a Walden FOM of 41.4 fJ/conv-step.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4854-4858"},"PeriodicalIF":4.0000,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An 800-MS/s 8.2-ENOB TDC-Assisted Pipelined-SAR ADC With Parallel Conversion\",\"authors\":\"Shao-Yu Wang;Tai-Cheng Lee\",\"doi\":\"10.1109/TCSII.2024.3445653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents a ring amplifier embedded with the time-to-digital converter (TDC) to implement parallel conversion techniques in a pipelined-SAR ADC. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This technique need no additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. Fabricated in a 28-nm CMOS technology, the ADC achieves a 45.06-dB SNDR at 800 MS/s and consumes 4.84 mW with a 0.9-V supply, yielding a Walden FOM of 41.4 fJ/conv-step.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"71 12\",\"pages\":\"4854-4858\"},\"PeriodicalIF\":4.0000,\"publicationDate\":\"2024-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10638764/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10638764/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本简介介绍了一种嵌入时域数字转换器(TDC)的环形放大器,用于在流水线式 SAR ADC 中实现并行转换技术。环形放大器作为残差放大器,在为时域量化器提供信息方面起着至关重要的作用。该技术在应用并行转换技术时无需额外的复杂电路和电容器,从而将采样率提高了 20%。ADC 采用 28 纳米 CMOS 技术制造,在 800 MS/s 时实现了 45.06 分贝的 SNDR,在 0.9 V 电源下的功耗为 4.84 mW,沃顿 FOM 为 41.4 fJ/conv-step。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 800-MS/s 8.2-ENOB TDC-Assisted Pipelined-SAR ADC With Parallel Conversion
This brief presents a ring amplifier embedded with the time-to-digital converter (TDC) to implement parallel conversion techniques in a pipelined-SAR ADC. The ring amplifier, functioning as the residue amplifier, has a crucial role of providing information for the time-domain quantizer. This technique need no additional complex circuits and capacitors for applying parallel conversion techniques, resulting in 20% sampling rate boost. Fabricated in a 28-nm CMOS technology, the ADC achieves a 45.06-dB SNDR at 800 MS/s and consumes 4.84 mW with a 0.9-V supply, yielding a Walden FOM of 41.4 fJ/conv-step.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程:电子与电气
CiteScore
7.90
自引率
20.50%
发文量
883
审稿时长
3.0 months
期刊介绍: TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信