Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang
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Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a \n<inline-formula> <tex-math>$2.3\\times $ </tex-math></inline-formula>\n performance speedup and \n<inline-formula> <tex-math>$2.7\\times $ </tex-math></inline-formula>\n hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. Additionally, it achieves a \n<inline-formula> <tex-math>$2.4\\times $ </tex-math></inline-formula>\n performance speedup and \n<inline-formula> <tex-math>$3.2\\times $ </tex-math></inline-formula>\n improvements on hardware efficiency for the decryption core.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5004-5008"},"PeriodicalIF":4.0000,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography\",\"authors\":\"Yushu Yang;Zihang Wang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang\",\"doi\":\"10.1109/TCSII.2024.3451971\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Lattice-based cryptography has experienced significant advancements in recent years due to its versatility and simplicity. The ring learning with errors (RLWE) problem is widely adopted in lattice-based cryptography. However, the polynomial multiplication is the performance bottleneck of RLWE-based cryptography, which requires further examination. In this brief, a lightweight and efficient encryption/decryption coprocessor for RLWE-based cryptography is proposed. The time complexity of the Schoolbook polynomial multiplication (SPM) is reduced from \\n<inline-formula> <tex-math>${n}^{2}$ </tex-math></inline-formula>\\n to \\n<inline-formula> <tex-math>$ {n}^{ {2}} {/8}$ </tex-math></inline-formula>\\n by enhancing multiplication parallelism. Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a \\n<inline-formula> <tex-math>$2.3\\\\times $ </tex-math></inline-formula>\\n performance speedup and \\n<inline-formula> <tex-math>$2.7\\\\times $ </tex-math></inline-formula>\\n hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. 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A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography
Lattice-based cryptography has experienced significant advancements in recent years due to its versatility and simplicity. The ring learning with errors (RLWE) problem is widely adopted in lattice-based cryptography. However, the polynomial multiplication is the performance bottleneck of RLWE-based cryptography, which requires further examination. In this brief, a lightweight and efficient encryption/decryption coprocessor for RLWE-based cryptography is proposed. The time complexity of the Schoolbook polynomial multiplication (SPM) is reduced from
${n}^{2}$
to
$ {n}^{ {2}} {/8}$
by enhancing multiplication parallelism. Moreover, an optimized structure for the Compressed cumulative distribution table (CDT) Gaussian sampler is proposed, resulting in 22.2% reduction in storage resource. The proposed SPM structure demonstrates a
$2.3\times $
performance speedup and
$2.7\times $
hardware efficiency for the encryption core, compared with state-of-the-art SPM accelerators. Additionally, it achieves a
$2.4\times $
performance speedup and
$3.2\times $
improvements on hardware efficiency for the decryption core.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.