LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators

Integer polynomial multiplication has been frequently used in post-quantum cryptography and fully homomorphic encryption systems. Particularly, there exists a special polynomial multiplication, where the polynomial degree can be a power of two and the coefficients of the two input polynomials are unequal-sized (difficult to deploy fast algorithm for implementation efficiency). Following this direction, in this brief, we propose a novel hardware-implemented Lightweight and Timing-Efficient (LTE) integer polynomial multiplication design framework. We proposed two new algorithms for efficient implementation of the targeted polynomial multiplication. Accordingly, we presented two hardware accelerators with the help of several new hardware design techniques. The final implementation showcases the proposed accelerators’ superior performance, e.g., the proposed Accelerator-I $(v=512)$ has 44.7% less equivalent area-delay product (EADP) than the state-of-the-art design for $n=4,096$ , while the proposed Accelerator-II has at least 38.7% less ADP than the competing designs for $n=1,024$ . The proposed strategy is highly efficient and can be extended for other usage.