Dynamic Voltage Balancing Across Series-Connected 10 kV SiC JBS Diodes in Medium Voltage 3L-NPC Power Converter Having Snubberless Series-Connected 10 kV SiC MOSFETs

This article addresses the mitigation of dynamic voltage imbalance in series-connected 10 kV silicon carbide (SiC) JBS diodes within a three-level NPC (3L-NPC) converter using active turn- off delay control across complementary series-connected 10 kV SiC mosfet s. The implementation of active turn- off delay control in SiC mosfet s eliminates the need for passive $RC$ snubbers, which otherwise increase the switching $dv/dt$ mismatch and snubber current across the diodes. In addition, parasitic base-plate capacitance across mosfet s and diodes, along with parasitic bus bar and snubber inductance in the commutation path, contribute to turn- off voltage mismatch and snubber loss in series-connected 10 kV SiC JBS diodes. The mismatch in nonlinear capacitance of series-connected devices ( mosfet s and diodes) and the nonlinear mosfet $i$ $-$ $v_{gs}$ curve affect the turn- on and turn- off voltage transitions between complementary switching mosfet s and diodes, leading to variations in turn- off voltage mismatch and snubber losses. The 3L-NPC converter has eight types of switching transition, complicating the analysis of $RC$ snubber design. This complexity is further increased by nonlinear device parameters, parasitic capacitance, and inductance in the commutation path for each of the eight 10 kV SiC mosfet s and four 10 kV SiC JBS diodes. To address these challenges, this research develops a mathematical model for the switching transition between 10 kV SiC mosfet s and complementary 10 kV SiC JBS diodes in a two-level clamped inductive switching (CIS) test setup. The model considers the effects of parasitic base-plate capacitance and the absence of an $RC$ snubber due to active turn- off delay control across series-connected SiC mosfet s. Subsequently, the mathematical model is refined using an iterative algorithm to account for mismatches in nonlinear device capacitance of mosfet s and diodes, as well as the nonlinear $i$ $-$ $v_{gs}$ curve of mosfet s during the switching transition of the diode. This refined model is then used to design the $RC$ snubber for series-connected 10 kV SiC JBS diodes and to optimize the turn- on gate resistance of complementary 10 kV SiC mosfet s on two-level CIS test benches (TB1 and TB2). Following this, the design parameters are systematically adjusted using experimental results from 3L-NPC test benches 3 to 5. This article provides simplified steps for the design and analysis of the $RC$ snubber in various test benches, validated by experimental data. The 3L-NPC converter with the final $RC$ snubber design achieved 99.2% efficiency and a 35 V turn- off voltage mismatch. The maximum error between the theoretical model and experimental data is 4.8%.