High performance rapid single-flux-quantum bit-slice arithmetic logic unit

Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2ⁿ-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2ⁿ-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm² Nb/AlO_x/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 $\times$ 0.81 mm². All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86$\%$ - 104$\%$. The ALU achieves a 100$\%$ utilization rate, regardless of carry/borrow read-after-write correlations between instructions.