A 1.5–2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of −138 dBc/Hz at 1-MHz Offset Frequency

This letter presents a low phase noise wideband fractional-N fast-locking charge pump phase-locked loop (CPPLL) with a time-to-digital converter (TDC) calibrated by a frequency-locked loop (FLL). The proposed TDC loop is activated to adjust the PLL’s loop bandwidth (LBW) and accelerate the locking process. After the PLL locks, the TDC loop is automatically turned off, which does not require additional power and not affect the phase noise. Fabricated in the 65-nm CMOS process with an active area of 1.25 mm2, the proposed PLL achieves a phase noise of −138.55 dBc/Hz at 1-MHz offset from a 1.85-GHz carrier. It draws 54.2-mW power with a 50-MHz reference frequency from a 3.3-V power supply, leading to a −237.7-dB FoMr.