A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than $70$° phase margin and more than $10\mathrm{dB}$ gain margin with a load capacitor range of 0 to $500\mathrm{pF}$ and consumes less quiescent current. The proposed OTA uses a smaller SMC of $2\mathrm{pF}$ to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC $90\mathrm{nm}$ CMOS technology with BSIM4 MOSFETs.