Carlos Alfredo Pelcastre Ortega, Mónico Linares Aranda
{"title":"沙漏晶体管一种可抵御全电离剂量辐射的替代性改进 MOS 结构","authors":"Carlos Alfredo Pelcastre Ortega, Mónico Linares Aranda","doi":"10.1016/j.mejo.2024.106391","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents a novel MOSFET layout named the “hourglass transistor”, aimed to improve its electrical behavior under Total Ionizing Dose (TID) effects. The new radiation-tolerant device is based on augmenting parasitic channel resistance, alteration of the electric field by the longitudinal corner effect (LCE), and reducing channel resistance within the central gate region. The radiation-robust MOS structure design was implemented in a 130 nm CMOS bulk process and its performance was analyzed through simulations using 3D physical models. The proposed hourglass transistor was compared with rectangular, diamond, dog bone and H-gate devices, showing a reduction in the post-radiation <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> current of 8.77, 4.6, 1.85 and 13.7 times, respectively; and a pre-radiation normalized saturation current of 2.29, 1.04, 1.58 and 1.52 times greater with an increase of 4.84, 1, 2.47 and 2.03 times the gate area, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hourglass transistor: An alternative and improved MOS structure robust to total ionization dose radiation\",\"authors\":\"Carlos Alfredo Pelcastre Ortega, Mónico Linares Aranda\",\"doi\":\"10.1016/j.mejo.2024.106391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper presents a novel MOSFET layout named the “hourglass transistor”, aimed to improve its electrical behavior under Total Ionizing Dose (TID) effects. The new radiation-tolerant device is based on augmenting parasitic channel resistance, alteration of the electric field by the longitudinal corner effect (LCE), and reducing channel resistance within the central gate region. The radiation-robust MOS structure design was implemented in a 130 nm CMOS bulk process and its performance was analyzed through simulations using 3D physical models. The proposed hourglass transistor was compared with rectangular, diamond, dog bone and H-gate devices, showing a reduction in the post-radiation <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> current of 8.77, 4.6, 1.85 and 13.7 times, respectively; and a pre-radiation normalized saturation current of 2.29, 1.04, 1.58 and 1.52 times greater with an increase of 4.84, 1, 2.47 and 2.03 times the gate area, respectively.</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S187923912400095X\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S187923912400095X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Hourglass transistor: An alternative and improved MOS structure robust to total ionization dose radiation
This paper presents a novel MOSFET layout named the “hourglass transistor”, aimed to improve its electrical behavior under Total Ionizing Dose (TID) effects. The new radiation-tolerant device is based on augmenting parasitic channel resistance, alteration of the electric field by the longitudinal corner effect (LCE), and reducing channel resistance within the central gate region. The radiation-robust MOS structure design was implemented in a 130 nm CMOS bulk process and its performance was analyzed through simulations using 3D physical models. The proposed hourglass transistor was compared with rectangular, diamond, dog bone and H-gate devices, showing a reduction in the post-radiation current of 8.77, 4.6, 1.85 and 13.7 times, respectively; and a pre-radiation normalized saturation current of 2.29, 1.04, 1.58 and 1.52 times greater with an increase of 4.84, 1, 2.47 and 2.03 times the gate area, respectively.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.