Zhiteng Chao , Xindi Zhang , Junying Huang , Zizhen Liu , Yixuan Zhao , Jing Ye , Shaowei Cai , Huawei Li , Xiaowei Li
{"title":"使用嵌入 DFT 流程的专用 Pure MaxSAT 求解器的快速测试压实方法","authors":"Zhiteng Chao , Xindi Zhang , Junying Huang , Zizhen Liu , Yixuan Zhao , Jing Ye , Shaowei Cai , Huawei Li , Xiaowei Li","doi":"10.1016/j.vlsi.2024.102265","DOIUrl":null,"url":null,"abstract":"<div><p>Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102265"},"PeriodicalIF":2.2000,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow\",\"authors\":\"Zhiteng Chao , Xindi Zhang , Junying Huang , Zizhen Liu , Yixuan Zhao , Jing Ye , Shaowei Cai , Huawei Li , Xiaowei Li\",\"doi\":\"10.1016/j.vlsi.2024.102265\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.</p></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"100 \",\"pages\":\"Article 102265\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-08-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926024001299\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024001299","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow
Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.