{"title":"量子约束效应对包含源极/漏极耗尽区的无结环绕栅纳米片 NMOSFET 的阈值电压和漏极诱导的势垒降低效应的影响","authors":"Lijun Xu, Linfang An, Jia Zhao, Yulei He, Lijuan Teng, Yuanxing Jiang","doi":"10.1016/j.mejo.2024.106392","DOIUrl":null,"url":null,"abstract":"<div><p>In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions\",\"authors\":\"Lijun Xu, Linfang An, Jia Zhao, Yulei He, Lijuan Teng, Yuanxing Jiang\",\"doi\":\"10.1016/j.mejo.2024.106392\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124000961\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000961","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions
In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.