带共享自干扰消除器的增强线性宽带全双工接收器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Fan Chen;Wei Li;Chuangguo Wang;Yunyou Pu;Xingyu Ma;Shijiao Dong;Yun Wang;Hongtao Xu
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引用次数: 0

摘要

在 40 纳米 CMOS 工艺中实现了具有增强线性技术和共享自干扰消除(SIC)功能的宽带全双工(FD)接收器。通过将基于希尔伯特变换均衡(HTE)的自干扰(SI)消除器与平移环路相结合,提出了一种具有射频域消除功能的 FD 接收器,并通过在平移环路中重复使用混频器提供了一条额外的辅助消除路径。通过引入辅助路径,SI 电路对接收器前端的影响降到了最低。同时,还提出了一种可接受噪声衰减和额外功耗的自加载线性化技术,可在 FD 接收器中同时用于接收器和 SI 消除器。由于采用了二维调节,这种技术可以实现相对稳健的线性改进,并为电路设计带来灵活性。测量结果表明,建议的 FD 接收器工作频率为 0.8-3.5 GHz,增益为 29.0-31.8 dB,噪声系数为 3.68-5.23 dB。所提出的线性化技术使接收器的线性度提高了 3.2-4.7 分贝,而噪声系数仅降低了 0.45-0.64 分贝。此外,采用拟议线性化方法的消除器可实现 1.59 至 4.03 ns 的射频域延迟,同时线性度提高了 6.33 分贝。采用自加载技术和共享 SIC 后,在基于环行器的设置中,本研究中的 SIC 方案在 40-MHz 带宽 (BW) 上使用 64-QAM 调制信号测得的射频域 SI 抑制大于 23.4dB,RX 噪声衰减小于 1.38dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller
A wideband full-duplex (FD) receiver with enhanced-linearity technique and shared self-interference cancellation (SIC) is implemented in a 40-nm CMOS process. By combining Hilbert-transform-equalization (HTE)-based self-interference (SI) canceller and translational loop, an FD receiver with RF domain cancellation is presented with an extra auxiliary cancellation path by reusing the mixer in the translational loop. By introducing the auxiliary path, the influence of SI circuit to receiver front end is minimized. Meanwhile, a self-loaded linearization technique with acceptable noise degradation and extra power consumption is proposed to be employed in the FD receiver for both receiver and SI canceller. Due to the 2-D regulation, such a technique can achieve a relatively robust linearity improvement and bring flexibility to circuit design. The measurement results show that the proposed FD receiver operates across 0.8–3.5 GHz with a gain of 29.0–31.8 dB and a noise figure of 3.68–5.23 dB. The proposed linearization technique achieves 3.2–4.7-dB linearity improvement for receiver with only 0.45–0.64-dB NF degradation. In addition, the canceller with the proposed linearization method achieves RF domain delays ranging from 1.59 to 4.03 ns while demonstrating more than 6.33-dB linearity improvement. With the implementation of self-loaded technique and shared SIC, a greater than 23.4-dB RF domain SI suppression is measured across 40-MHz bandwidth (BW) with 64-QAM modulated signals in a circulator-based setup for the SIC scheme in this work with RX noise degradation of less than 1.38 dB.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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