Fan Chen;Wei Li;Chuangguo Wang;Yunyou Pu;Xingyu Ma;Shijiao Dong;Yun Wang;Hongtao Xu
{"title":"带共享自干扰消除器的增强线性宽带全双工接收器","authors":"Fan Chen;Wei Li;Chuangguo Wang;Yunyou Pu;Xingyu Ma;Shijiao Dong;Yun Wang;Hongtao Xu","doi":"10.1109/TVLSI.2024.3410010","DOIUrl":null,"url":null,"abstract":"A wideband full-duplex (FD) receiver with enhanced-linearity technique and shared self-interference cancellation (SIC) is implemented in a 40-nm CMOS process. By combining Hilbert-transform-equalization (HTE)-based self-interference (SI) canceller and translational loop, an FD receiver with RF domain cancellation is presented with an extra auxiliary cancellation path by reusing the mixer in the translational loop. By introducing the auxiliary path, the influence of SI circuit to receiver front end is minimized. Meanwhile, a self-loaded linearization technique with acceptable noise degradation and extra power consumption is proposed to be employed in the FD receiver for both receiver and SI canceller. Due to the 2-D regulation, such a technique can achieve a relatively robust linearity improvement and bring flexibility to circuit design. The measurement results show that the proposed FD receiver operates across 0.8–3.5 GHz with a gain of 29.0–31.8 dB and a noise figure of 3.68–5.23 dB. The proposed linearization technique achieves 3.2–4.7-dB linearity improvement for receiver with only 0.45–0.64-dB NF degradation. In addition, the canceller with the proposed linearization method achieves RF domain delays ranging from 1.59 to 4.03 ns while demonstrating more than 6.33-dB linearity improvement. With the implementation of self-loaded technique and shared SIC, a greater than 23.4-dB RF domain SI suppression is measured across 40-MHz bandwidth (BW) with 64-QAM modulated signals in a circulator-based setup for the SIC scheme in this work with RX noise degradation of less than 1.38 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller\",\"authors\":\"Fan Chen;Wei Li;Chuangguo Wang;Yunyou Pu;Xingyu Ma;Shijiao Dong;Yun Wang;Hongtao Xu\",\"doi\":\"10.1109/TVLSI.2024.3410010\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wideband full-duplex (FD) receiver with enhanced-linearity technique and shared self-interference cancellation (SIC) is implemented in a 40-nm CMOS process. By combining Hilbert-transform-equalization (HTE)-based self-interference (SI) canceller and translational loop, an FD receiver with RF domain cancellation is presented with an extra auxiliary cancellation path by reusing the mixer in the translational loop. By introducing the auxiliary path, the influence of SI circuit to receiver front end is minimized. Meanwhile, a self-loaded linearization technique with acceptable noise degradation and extra power consumption is proposed to be employed in the FD receiver for both receiver and SI canceller. Due to the 2-D regulation, such a technique can achieve a relatively robust linearity improvement and bring flexibility to circuit design. The measurement results show that the proposed FD receiver operates across 0.8–3.5 GHz with a gain of 29.0–31.8 dB and a noise figure of 3.68–5.23 dB. The proposed linearization technique achieves 3.2–4.7-dB linearity improvement for receiver with only 0.45–0.64-dB NF degradation. In addition, the canceller with the proposed linearization method achieves RF domain delays ranging from 1.59 to 4.03 ns while demonstrating more than 6.33-dB linearity improvement. With the implementation of self-loaded technique and shared SIC, a greater than 23.4-dB RF domain SI suppression is measured across 40-MHz bandwidth (BW) with 64-QAM modulated signals in a circulator-based setup for the SIC scheme in this work with RX noise degradation of less than 1.38 dB.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10555545/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10555545/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller
A wideband full-duplex (FD) receiver with enhanced-linearity technique and shared self-interference cancellation (SIC) is implemented in a 40-nm CMOS process. By combining Hilbert-transform-equalization (HTE)-based self-interference (SI) canceller and translational loop, an FD receiver with RF domain cancellation is presented with an extra auxiliary cancellation path by reusing the mixer in the translational loop. By introducing the auxiliary path, the influence of SI circuit to receiver front end is minimized. Meanwhile, a self-loaded linearization technique with acceptable noise degradation and extra power consumption is proposed to be employed in the FD receiver for both receiver and SI canceller. Due to the 2-D regulation, such a technique can achieve a relatively robust linearity improvement and bring flexibility to circuit design. The measurement results show that the proposed FD receiver operates across 0.8–3.5 GHz with a gain of 29.0–31.8 dB and a noise figure of 3.68–5.23 dB. The proposed linearization technique achieves 3.2–4.7-dB linearity improvement for receiver with only 0.45–0.64-dB NF degradation. In addition, the canceller with the proposed linearization method achieves RF domain delays ranging from 1.59 to 4.03 ns while demonstrating more than 6.33-dB linearity improvement. With the implementation of self-loaded technique and shared SIC, a greater than 23.4-dB RF domain SI suppression is measured across 40-MHz bandwidth (BW) with 64-QAM modulated signals in a circulator-based setup for the SIC scheme in this work with RX noise degradation of less than 1.38 dB.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.