Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Cryptography is crucial in embedded systems for safeguarding sensitive information, maintaining data integrity, and facilitating secure communication. L1 cache memory enhances overall performance by temporarily storing cryptographic keys. Post-quantum cryptography (PQC) focuses on creating algorithms that stay secure even against quantum computing threats. However, PQC doesn't fully protect against side-channel attacks (SCA). As IoT devices like wearable health monitors and industrial sensors become more widespread, the demand for lightweight cryptography increases to balance security with resource constraints. Yet, lightweight cryptography can face challenges, including reduced security and increased susceptibility to SCA due to smaller key sizes. Attackers can exploit power consumption patterns through side-channel attacks (SCA), such as Power Analysis, to extract these secret keys. Once a key is compromised, encrypted data becomes vulnerable. In cloud computing cache side-channel attacks take advantage of multiple virtual machines running simultaneously on the same hardware, enabling them to extract sensitive information from encryption processes. Although many SRAM cells have been designed in the literature, none offer complete security against SCA. This paper presents a new architecture for secure cache memory using a proposed 10T SRAM cell that secures all three cell operations (read, write, and hold) against SCA attacks. Additionally, this architecture also prevents half selection issue in cache memory. The security measure of proposed-10T cell is 97.19 % which is highest among all other cells and reliability measure is 82.03 %.The cell also offers highest hold stability of 421 mV along with good read stability and write ability of 220 mV and 334 mV respectively. The leakage of Proposed-10T cell is also less i.e., 13.56 pA. The Performance and Security Factor (PSF) is computed for all considered cells, encompassing various performance and security metrics. The normalized PSF (PSF)_N of the Proposed-10T cell is 2.17, the highest among all cells considered for comparison. Therefore, the Proposed-10T cell architecture is fully secure against SCA and achieves better performance during cell operations.