Efficient deployment of Single Shot Multibox Detector network on FPGAs

FPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. However, contemporary FPGA designs often come with high costs and resource demands, which limit their adoption in resource-constrained embedded and edge devices. This study presents a novel design that addresses these limitations by emphasizing cost-effectiveness, energy efficiency, and rapid performance, particularly for single-shot multi-box detectors. The design employs an Xilinx ZYNQ7020-based main control chip and leverages parallel computing models for convolution layers and feature extraction. It enhances efficiency by proposing parallel feature extraction at the network architecture level and integrates convolution activation and pooling in a single, hardware-optimized operation for convolution kernel computations. The design employs alternating memory reuse for feature layer inputs and outputs to optimize memory management, thereby reducing read/write delays and transmission times. Implemented on a PYNQ-Z2 development board and tested using Jupyter Notebook, the SSD algorithm demonstrates a 789.4 GOPS inference performance with 16-bit fixed-point quantization at a 200MHz clock frequency, achieving an average accuracy of 77.84% and an inference time of 81.4621 ms, while consuming 1.595 watts of power. This innovative design significantly boosts energy efficiency by up to 2590%, outperforming contemporary methods.