A high-speed dynamic comparator with automatic offset calibration

A high-speed dynamic comparator with preamplifier and automatic dc offset calibration in all stages is proposed in this paper. The offset compensation is applied in two stages, following a two-part sequential loop training topology, offering significant reduction of the dc offset in each stage. The final resolution is improved with a final value less than 800 μV operating at 7.5 GHz clock speed. The dynamic comparator stage is a double-tail topology while the calibration topology is based on a current injection technique, instead of the commonly used capacitive calibration which can reduce the operating speed. Designed in a CMOS 65 nm technology node, the circuit operates with 1 V supply voltage. Results of PVT Monte Carlo post-layout simulations verify the operation of the proposed topology.